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/linux-6.12.1/Documentation/devicetree/bindings/display/msm/
Dqcom,sm6350-mdss.yaml102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
124 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,sc8280xp-dpu.yaml69 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
78 assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
Dqcom,sc8280xp-mdss.yaml72 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
103 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
Dqcom,sm6125-mdss.yaml95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,sm6375-mdss.yaml93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,sm6115-mdss.yaml95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
113 <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,qcm2290-mdss.yaml98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
122 <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,sm8350-mdss.yaml109 <&dispcc DISP_CC_MDSS_MDP_CLK>;
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,sdm670-mdss.yaml96 <&dispcc DISP_CC_MDSS_MDP_CLK>;
123 <&dispcc DISP_CC_MDSS_MDP_CLK>,
Dqcom,sdm845-mdss.yaml99 <&dispcc DISP_CC_MDSS_MDP_CLK>;
119 <&dispcc DISP_CC_MDSS_MDP_CLK>,
/linux-6.12.1/drivers/clk/qcom/
Ddispcc-qcm2290.c340 static struct clk_branch disp_cc_mdss_mdp_clk = { variable
347 .name = "disp_cc_mdss_mdp_clk",
474 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
Ddispcc-sm6375.c335 static struct clk_branch disp_cc_mdss_mdp_clk = { variable
342 .name = "disp_cc_mdss_mdp_clk",
526 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
Ddispcc-sm6115.c389 static struct clk_branch disp_cc_mdss_mdp_clk = { variable
396 .name = "disp_cc_mdss_mdp_clk",
539 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
Ddispcc-sm6125.c488 static struct clk_branch disp_cc_mdss_mdp_clk = { variable
495 .name = "disp_cc_mdss_mdp_clk",
635 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
Ddispcc-sc7180.c501 static struct clk_branch disp_cc_mdss_mdp_clk = { variable
508 .name = "disp_cc_mdss_mdp_clk",
662 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
/linux-6.12.1/include/dt-bindings/clock/
Dqcom,dispcc-qcm2290.h19 #define DISP_CC_MDSS_MDP_CLK 9 macro
Dqcom,sm6115-dispcc.h20 #define DISP_CC_MDSS_MDP_CLK 10 macro
Dqcom,sm6375-dispcc.h20 #define DISP_CC_MDSS_MDP_CLK 9 macro
Dqcom,dispcc-sm6125.h26 #define DISP_CC_MDSS_MDP_CLK 17 macro
Dqcom,dispcc-sc7180.h29 #define DISP_CC_MDSS_MDP_CLK 20 macro
Dqcom,dispcc-sm6350.h30 #define DISP_CC_MDSS_MDP_CLK 19 macro
Dqcom,sm4450-dispcc.h20 #define DISP_CC_MDSS_MDP_CLK 10 macro
Dqcom,dispcc-sc7280.h37 #define DISP_CC_MDSS_MDP_CLK 27 macro
Dqcom,dispcc-sdm845.h22 #define DISP_CC_MDSS_MDP_CLK 12 macro
Dqcom,dispcc-sm8150.h42 #define DISP_CC_MDSS_MDP_CLK 32 macro

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