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/linux-6.12.1/Documentation/devicetree/bindings/display/msm/
Dqcom,sm8550-mdss.yaml102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
126 <&dispcc DISP_CC_MDSS_AHB_CLK>,
202 <&dispcc DISP_CC_MDSS_AHB_CLK>,
274 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
291 <&dispcc DISP_CC_MDSS_AHB_CLK>,
344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sm8150-mdss.yaml105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
198 <&dispcc DISP_CC_MDSS_AHB_CLK>,
270 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
288 <&dispcc DISP_CC_MDSS_AHB_CLK>,
341 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sm8250-mdss.yaml108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
201 <&dispcc DISP_CC_MDSS_AHB_CLK>,
273 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
291 <&dispcc DISP_CC_MDSS_AHB_CLK>,
344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sm8450-mdss.yaml105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
210 <&dispcc DISP_CC_MDSS_AHB_CLK>,
287 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
305 <&dispcc DISP_CC_MDSS_AHB_CLK>,
358 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sdm670-mdss.yaml121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
164 <&dispcc DISP_CC_MDSS_AHB_CLK>,
216 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
234 <&dispcc DISP_CC_MDSS_AHB_CLK>,
286 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sdm845-mdss.yaml117 <&dispcc DISP_CC_MDSS_AHB_CLK>,
160 <&dispcc DISP_CC_MDSS_AHB_CLK>,
212 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
230 <&dispcc DISP_CC_MDSS_AHB_CLK>,
282 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sm6125-mdss.yaml94 <&dispcc DISP_CC_MDSS_AHB_CLK>,
118 <&dispcc DISP_CC_MDSS_AHB_CLK>,
162 <&dispcc DISP_CC_MDSS_AHB_CLK>,
214 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sm6375-mdss.yaml92 <&dispcc DISP_CC_MDSS_AHB_CLK>,
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
160 <&dispcc DISP_CC_MDSS_AHB_CLK>,
213 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sc7280-mdss.yaml115 <&dispcc DISP_CC_MDSS_AHB_CLK>,
142 <&dispcc DISP_CC_MDSS_AHB_CLK>,
197 <&dispcc DISP_CC_MDSS_AHB_CLK>,
269 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
289 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
380 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sc7180-mdss.yaml105 <&dispcc DISP_CC_MDSS_AHB_CLK>,
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
174 <&dispcc DISP_CC_MDSS_AHB_CLK>,
245 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
263 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sm6350-mdss.yaml121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
132 <&dispcc DISP_CC_MDSS_AHB_CLK>;
168 <&dispcc DISP_CC_MDSS_AHB_CLK>,
221 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
Dqcom,sm6115-mdss.yaml112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
150 <&dispcc DISP_CC_MDSS_AHB_CLK>,
199 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
Dqcom,qcm2290-mdss.yaml121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
159 <&dispcc DISP_CC_MDSS_AHB_CLK>,
210 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
Dqcom,sm8350-mdss.yaml106 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_AHB_CLK>,
199 <&dispcc DISP_CC_MDSS_AHB_CLK>,
Dqcom,sc8280xp-mdss.yaml71 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
101 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
/linux-6.12.1/drivers/clk/qcom/
Ddispcc-qcm2290.c268 static struct clk_branch disp_cc_mdss_ahb_clk = { variable
275 .name = "disp_cc_mdss_ahb_clk",
466 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
Ddispcc-sm6375.c263 static struct clk_branch disp_cc_mdss_ahb_clk = { variable
270 .name = "disp_cc_mdss_ahb_clk",
518 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
Ddispcc-sm6115.c317 static struct clk_branch disp_cc_mdss_ahb_clk = { variable
324 .name = "disp_cc_mdss_ahb_clk",
531 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
Ddispcc-sm6125.c326 static struct clk_branch disp_cc_mdss_ahb_clk = { variable
333 .name = "disp_cc_mdss_ahb_clk",
619 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
/linux-6.12.1/include/dt-bindings/clock/
Dqcom,dispcc-qcm2290.h11 #define DISP_CC_MDSS_AHB_CLK 1 macro
Dqcom,sm6115-dispcc.h12 #define DISP_CC_MDSS_AHB_CLK 2 macro
Dqcom,sm6375-dispcc.h12 #define DISP_CC_MDSS_AHB_CLK 1 macro
Dqcom,dispcc-sm6125.h10 #define DISP_CC_MDSS_AHB_CLK 1 macro
Dqcom,dispcc-sc7180.h11 #define DISP_CC_MDSS_AHB_CLK 2 macro
Dqcom,dispcc-sm6350.h12 #define DISP_CC_MDSS_AHB_CLK 1 macro

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