Searched full:ddr3 (Results 1 – 25 of 79) sorted by relevance
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | rk3399-ddr.h | 7 * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
11 /* DDR3-800 (5-5-5) */
13 /* DDR3-800 (6-6-6) */
15 /* DDR3-1066 (6-6-6) */
17 /* DDR3-1066 (7-7-7) */
19 /* DDR3-1066 (8-8-8) */
21 /* DDR3-1333 (7-7-7) */
23 /* DDR3-1333 (8-8-8) */
25 /* DDR3-1333 (9-9-9) */
27 /* DDR3-1333 (10-10-10) */
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 52 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
53 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
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| D | renesas,dbsc.yaml | 15 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
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| /linux-6.12.1/drivers/clk/axis/ |
| D | clk-artpec6.c | 67 case 0: /* DDR3-2133 mode */ in of_artpec6_clkctrl_setup()
71 case 1: /* DDR3-1866 mode */ in of_artpec6_clkctrl_setup()
75 case 2: /* DDR3-1600 mode */ in of_artpec6_clkctrl_setup()
79 case 3: /* DDR3-1333 mode */ in of_artpec6_clkctrl_setup()
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | sddr3.c | 48 /* the below are mentioned in some, but not all, ddr3 docs */
56 /* the below are mentioned in some, but not all, ddr3 docs */
64 /* the below are mentioned in some, but not all, ddr3 docs */
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| /linux-6.12.1/arch/sh/include/mach-common/mach/ |
| D | urquell.h | 11 * CS2 | DDR3
56 #define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
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| /linux-6.12.1/include/linux/ |
| D | edac.h | 174 * @MEM_DDR3: DDR3 RAM
175 * @MEM_RDDR3: Registered DDR3 RAM
176 * This is a variant of the DDR3 memories.
177 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
178 * @MEM_LPDDR3: Low-Power DDR3 memory.
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| /linux-6.12.1/drivers/edac/ |
| D | pnd2_edac.h | 221 u32 bg0 : 5; /* if ddr3, ba2 = bg0 */
222 u32 bg1 : 5; /* if ddr3, ba3 = bg1 */
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| D | ti_edac.c | 5 * Texas Instruments DDR3 ECC error correction and detection driver
335 MODULE_DESCRIPTION("EDAC Driver for Texas Instruments DDR3 MC");
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| D | edac_mc.c | 155 [MEM_DDR3] = "Unbuffered-DDR3",
156 [MEM_RDDR3] = "Registered-DDR3",
157 [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM",
158 [MEM_LPDDR3] = "Low-Power-DDR3-RAM",
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| /linux-6.12.1/arch/arm64/boot/dts/marvell/ |
| D | armada-3720-db.dts | 4 * (DB-88F3720-DDR3)
20 model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
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| D | armada-3720-uDPU.dtsi | 4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,hr2.yaml | 12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
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| D | brcm,nsp.yaml | 14 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
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| /linux-6.12.1/Documentation/devicetree/bindings/edac/ |
| D | aspeed-sdram-edac.txt | 3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
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| /linux-6.12.1/arch/powerpc/platforms/44x/ |
| D | fsp2.h | 127 /* DDR3/4 Memory Controller */
164 /* PLB-Attached DDR3/4 Core Wrapper */
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| /linux-6.12.1/Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
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| /linux-6.12.1/Documentation/devicetree/bindings/regulator/ |
| D | renesas,raa215300.yaml | 14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
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| /linux-6.12.1/drivers/memory/ |
| D | ti-emif-sram-pm.S | 224 * Output impedence calib needed only for DDR3
245 * configuration of the EMIF PHY, only for DDR3.
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
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| /linux-6.12.1/Documentation/hwmon/ |
| D | pxe1610.rst | 51 Used for DDR3/DDR4 Memory power regulation for Intel VR13 and
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| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | turris1x.dts | 60 /* DDR3 SPD/EEPROM PSWP instruction */
88 /* DDR3 SPD/EEPROM */
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| /linux-6.12.1/arch/arm/mach-bcm/ |
| D | Kconfig | 63 Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and
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| /linux-6.12.1/include/soc/at91/ |
| D | sama7-ddr.h | 3 * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets
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| /linux-6.12.1/arch/sh/boards/ |
| D | board-urquell.c | 44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
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