| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
20 Node to get DDR loading. Refer to
26 clock-names:
28 - const: dmc_clk
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| /linux-6.12.1/Documentation/driver-api/thermal/ |
| D | intel_dptf.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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| /linux-6.12.1/drivers/media/pci/cx18/ |
| D | cx18-cards.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-cards.c
11 #include "cx18-driver.h"
12 #include "cx18-cards.h"
13 #include "cx18-av-core.h"
14 #include "cx18-i2c.h"
38 /* Please add new PCI IDs to: https://pci-ids.ucw.cz/
43 /* Hauppauge HVR-1600 cards */
48 .type = CX18_CARD_HVR_1600_ESMT,
49 .name = "Hauppauge HVR-1600",
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| D | cx23418.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <media/drv-intf/cx2341x.h>
19 IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
21 OUT[0] - Task handle. This handle is passed along with commands to
23 ReturnCode - One of the ERR_SYS_... */
27 IN[0] - Task handle. Hanlde of the task to destroy
28 ReturnCode - One of the ERR_SYS_... */
49 IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?)
50 IN[1] - caller buffer address, or 0
51 ReturnCode - ??? */
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| /linux-6.12.1/drivers/edac/ |
| D | skx_common.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
60 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
67 * mmm = error type
72 * Errors from either the memory of the 1-level memory system or the
73 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
78 * of the 2-level memory system.
128 enum type { enum
183 enum type type; member
188 /* DDR memory controllers per socket */
190 /* DDR channels per DDR memory controller */
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| D | synopsys_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DDR ECC Driver
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
33 /* Synopsys DDR memory controller registers that are relevant to ECC */
89 /* DDR ECC Quirks */
94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
143 /* DDR Control Register width definitions */
160 /* DDR QOS Interrupt register definitions */
168 /* DDR QOS Interrupt register definitions */
193 /* DDR Memory type defines */
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| D | i10nm_base.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <asm/intel-family.h>
24 pci_read_config_dword((d)->uracu, 0xd0, &(reg))
26 pci_read_config_dword((d)->uracu, \
27 (res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg))
29 pci_read_config_dword((d)->sad_all, (offset) + (i) * \
30 (res_cfg->type == GNR ? 12 : 8), &(reg))
32 pci_read_config_dword((d)->uracu, 0xd4, &(reg))
34 pci_read_config_dword((d)->pcu_cr3, \
35 res_cfg->type == GNR ? 0x290 : 0x90, &(reg))
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| /linux-6.12.1/Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd9576-pmic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
35 controlled by a GPIO. This is dictated by state of vout1-en pin during
[all …]
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| D | rohm,bd9571mwv.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marek.vasut@gmail.com>
15 - rohm,bd9571mwv
16 - rohm,bd9574mwf
24 interrupt-controller: true
26 '#interrupt-cells':
29 gpio-controller: true
31 '#gpio-cells':
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| /linux-6.12.1/drivers/memory/ |
| D | of_memory.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
20 * @np: pointer to ddr device tree node
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
41 ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin); in of_get_min_tck()
42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
44 ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); in of_get_min_tck()
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| D | jedec_ddr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Definitions for DDR memories based on JEDEC specs
14 /* DDR Densities */
26 /* DDR type */
34 /* DDR IO width */
64 /* Refresh rate in nano-seconds */
135 /* Structure for DDR addressing info from the JEDEC spec */
171 * type
207 * -ENOENT if info unavailable.
254 * type
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| D | emif.c | 1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct emif_data - Per device static data for driver's use
34 * @duplicate: Whether the DDR devices attached to this EMIF
38 * to this EMIF - read from MR4 register. If there
43 * @base: base address of memory-mapped IO registers.
47 * frequencies, to avoid re-calculating them on
54 * @np_ddr: Pointer to ddr device tree node
77 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show() local
78 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
81 regs->freq/1000000); in do_emif_regdump_show()
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| D | renesas-rpc-if.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RPC-IF core driver
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
19 #include <memory/renesas-rpc-if.h>
43 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
111 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
120 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
128 #define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
129 #define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
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| /linux-6.12.1/include/linux/platform_data/ |
| D | emif_plat.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Low power modes - EMIF_PWR_MGMT_CTRL */
23 * EMIF4D - Used in OMAP4
24 * EMIF4D5 - Used in OMAP5
31 * ATTILAPHY - Used in OMAP4
32 * INTELLIPHY - Used in OMAP5
44 * struct ddr_device_info - All information about the DDR device except AC
46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
49 * @cs1_used: Whether there is a DDR device attached to the second
50 * chip-select(CS1) of this EMIF instance
[all …]
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| /linux-6.12.1/drivers/regulator/ |
| D | bd9571mwv-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ROHM BD9571MWV-M and BD9574MWF-M regulator driver
12 #include <linux/mfd/rohm-generic.h>
23 /* DDR Backup Power */
24 u8 bkup_mode_cnt_keepon; /* from "rohm,ddr-backup-power" */
28 /* Power switch type */
43 .type = REGULATOR_VOLTAGE, \
57 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_SET_MONI, &val); in bd9571mwv_avs_get_moni_state()
73 return regmap_write_bits(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), in bd9571mwv_avs_set_voltage_sel_regmap()
74 rdev->desc->vsel_mask, sel); in bd9571mwv_avs_set_voltage_sel_regmap()
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| /linux-6.12.1/Documentation/admin-guide/perf/ |
| D | alibaba_pmu.rst | 2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
30 - Group 1: PMU Bandwidth Counters. This group has 8 counters that are used
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| D | imx-ddr.rst | 2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
38 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
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| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
| D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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| /linux-6.12.1/drivers/devfreq/event/ |
| D | rockchip-dfi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
8 #include <linux/devfreq-event.h>
69 * struct dmc_count_channel - structure to hold counter values from the DDR controller
71 * @clock_cycles: DDR clock cycles
87 * The dfi controller can monitor DDR load. It has an upper and lower threshold
89 * generated to indicate the DDR frequency should be changed.
123 void __iomem *dfi_regs = dfi->regs; in rockchip_dfi_enable()
126 mutex_lock(&dfi->mutex); in rockchip_dfi_enable()
128 dfi->usecount++; in rockchip_dfi_enable()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
31 This add the devfreq-event driver for Exynos SoC. It provides PPMU
39 This add the devfreq-event driver for Rockchip SoC. It provides DFI
40 (DDR Monitor Module) driver to count ddr load.
|
| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dcsr.txt | 21 - compatible
23 Value type: <string>
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
29 Value type: <u32>
33 - #size-cells
35 Value type: <u32>
40 - ranges
42 Value type: <prop-encoded-array>
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| /linux-6.12.1/drivers/media/pci/tw5864/ |
| D | tw5864-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
17 /* DDR controller enabled */
30 * Video Frame mapping in DDR
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
145 /* DDR Single Access Page Number */
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/ |
| D | uncore-cache.json | 22 …"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory sta…
32 …"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
42 …"BriefDescription": "Counts only multi-socket cacheline Directory state updates memory writes issu…
52 …"BriefDescription": "Counts only multi-socket cacheline Directory state updates due to memory writ…
90 …"BriefDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA…
110 …"BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total num…
158 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
224 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
246 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
268 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
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| /linux-6.12.1/sound/soc/intel/atom/sst/ |
| D | sst.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * sst.c - Intel SST Driver for audio engine
5 * Copyright (C) 2008-14 Intel Corp
28 #include "../sst-mfld-platform.h"
57 isr.full = sst_shim_read64(drv->shim, SST_ISRX); in intel_sst_interrupt_mrfld()
61 spin_lock(&drv->ipc_spin_lock); in intel_sst_interrupt_mrfld()
62 header.full = sst_shim_read64(drv->shim, in intel_sst_interrupt_mrfld()
63 drv->ipc_reg.ipcx); in intel_sst_interrupt_mrfld()
65 sst_shim_write64(drv->shim, drv->ipc_reg.ipcx, header.full); in intel_sst_interrupt_mrfld()
69 sst_shim_write64(drv->shim, SST_ISRX, isr.full); in intel_sst_interrupt_mrfld()
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