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/linux-6.12.1/arch/m68k/ifpsp060/
Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/
Dhw_sequencer.h51 struct dc *dc; member
57 struct dc *dc; member
68 const struct dc *dc; member
74 struct dc *dc; member
79 struct dc *dc; member
107 struct dc *dc; member
113 struct dc *dc; member
145 const struct dc *dc; member
150 struct dc *dc; member
206 void (*hardware_release)(struct dc *dc);
[all …]
Dhw_sequencer_private.h75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*init_pipes)(struct dc *dc, struct dc_state *context);
78 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
79 void (*plane_atomic_disconnect)(struct dc *dc,
82 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
83 bool (*set_input_transfer_func)(struct dc *dc,
86 bool (*set_output_transfer_func)(struct dc *dc,
89 void (*power_down)(struct dc *dc);
92 bool (*enable_display_power_gating)(struct dc *dc,
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
Ddcn10_hwseq.h32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
59 struct dc *dc,
[all …]
/linux-6.12.1/drivers/dma/
Dtxx9dmac.c24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/
Ddc.c29 #include "dc.h"
90 dc->ctx
93 dc->ctx->logger
100 * DC is the OS-agnostic component of the amdgpu DC driver.
102 * DC maintains and validates a set of structs representing the state of the
105 * Main DC HW structs:
107 * struct dc - The central struct. One per driver. Created on driver load,
111 * Used as a backpointer by most other structs in dc.
124 * Main dc state structs:
127 * these structs in dc->current_state representing the currently programmed state.
[all …]
Ddc_link_exports.c27 * This file provides single entrance to link functionality declared in dc
32 * When exporting a new link related dc function, add function declaration in
33 * dc.h with detail interface documentation, then add function implementation
38 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) in dc_get_link_at_index() argument
43 return dc->links[link_index]; in dc_get_link_at_index()
46 void dc_get_edp_links(const struct dc *dc, in dc_get_edp_links() argument
53 for (i = 0; i < dc->link_count; i++) { in dc_get_edp_links()
55 if (!dc->links[i]) in dc_get_edp_links()
57 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) { in dc_get_edp_links()
58 edp_links[*edp_num] = dc->links[i]; in dc_get_edp_links()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
/linux-6.12.1/drivers/md/
Ddm-delay.c55 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
57 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
60 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
62 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
65 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
67 return !!dc->worker; in delay_is_fast()
82 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
91 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
92 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
93 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux-6.12.1/drivers/tty/
Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
Ddcn32_hwseq.c63 dc->ctx->logger
77 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control() local
79 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
82 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
168 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
197 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) in dcn32_check_no_memory_request_for_cab() argument
202 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
203 if ((dc->current_state->stream_status[i].plane_count) && in dcn32_check_no_memory_request_for_cab()
204 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) in dcn32_check_no_memory_request_for_cab()
209 if (i == dc->current_state->stream_count) in dcn32_check_no_memory_request_for_cab()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
Ddcn401_hwseq.h9 #include "dc.h"
14 struct dc;
36 void dcn401_init_hw(struct dc *dc);
40 bool dcn401_set_output_transfer_func(struct dc *dc,
43 void dcn401_trigger_3dlut_dma_load(struct dc *dc,
50 struct dc *dc);
52 void dcn401_populate_mcm_luts(struct dc *dc,
60 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
62 struct ips_ono_region_state dcn401_read_ono_state(struct dc *dc,
64 void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,
[all …]
Ddcn401_hwseq.c44 dc->ctx->logger
51 static void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
53 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
56 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
57 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
58 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
59 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
60 if (dc->debug.disable_boot_optimizations) { in dcn401_initialize_min_clocks()
61 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
68 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); in dcn401_initialize_min_clocks()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/
DMakefile39 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
40 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
41 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
42 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
43 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
44 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
45 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
46 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
47 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
48 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
Ddcn31_hwseq.c61 dc->ctx->logger
68 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
70 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
73 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
81 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
86 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
91 if (dc->debug.enable_mem_low_power.bits.mpc && in enable_memory_low_power()
92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
[all …]
/linux-6.12.1/drivers/md/bcache/
Dwriteback.c30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
48 div64_u64(bdev_nr_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT, in __calc_target_rate()
52 div_u64(cache_sectors * dc->writeback_percent, 100); in __calc_target_rate()
61 static void __update_writeback_rate(struct cached_dev *dc) in __update_writeback_rate() argument
83 int64_t target = __calc_target_rate(dc); in __update_writeback_rate()
84 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); in __update_writeback_rate()
87 div_s64(error, dc->writeback_rate_p_term_inverse); in __update_writeback_rate()
101 struct cache_set *c = dc->disk.c; in __update_writeback_rate()
105 if (dc->writeback_consider_fragment && in __update_writeback_rate()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
Ddcn35_hwseq.c76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
99 if (dc->debug.enable_mem_low_power.bits.mpc &&
100 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
103 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn401/
Ddcn401_fpu.c16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
62 if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { in dcn401_build_wm_range_table_fpu()
101 * - with passed few options from dc->config
104 * - with passed latency values (passed in ns units) in dc-> bb override for
114 void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box_fpu() argument
118 /* Override from passed dc->bb_overrides if available*/ in dcn401_update_bw_bounding_box_fpu()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c28 #include "dc.h"
40 dc->ctx->logger
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
500 // dc->dml.logger = pool->base.logger; in dcn_bw_calc_rq_dlg_ttu()
638 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
642 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
DMakefile38 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2
39 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_core
40 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_mcg/
41 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_dpmm/
42 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_pmo/
43 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_standalone_libraries/
44 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/inc
45 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/inc
46 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/
48 CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)
[all …]

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