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/linux-6.12.1/drivers/dma/
Dtxx9dmac.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/
Ddc.c29 #include "dc.h"
90 dc->ctx
93 dc->ctx->logger
95 static const char DC_BUILD_ID[] = "production-build";
100 * DC is the OS-agnostic component of the amdgpu DC driver.
102 * DC maintains and validates a set of structs representing the state of the
105 * Main DC HW structs:
107 * struct dc - The central struct. One per driver. Created on driver load,
110 * struct dc_context - One per driver.
111 * Used as a backpointer by most other structs in dc.
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Ddc_link_exports.c27 * This file provides single entrance to link functionality declared in dc
32 * When exporting a new link related dc function, add function declaration in
33 * dc.h with detail interface documentation, then add function implementation
38 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) in dc_get_link_at_index() argument
43 return dc->links[link_index]; in dc_get_link_at_index()
46 void dc_get_edp_links(const struct dc *dc, in dc_get_edp_links() argument
53 for (i = 0; i < dc->link_count; i++) { in dc_get_edp_links()
55 if (!dc->links[i]) in dc_get_edp_links()
57 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) { in dc_get_edp_links()
58 edp_links[*edp_num] = dc->links[i]; in dc_get_edp_links()
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Ddc_stream.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
28 #include "dc.h"
37 #define DC_LOGGER dc->ctx->logger
48 if (sink->sink_signal == SIGNAL_TYPE_NONE) in update_stream_signal()
49 stream->signal = stream->link->connector_signal; in update_stream_signal()
51 stream->signal = sink->sink_signal; in update_stream_signal()
53 if (dc_is_dvi_signal(stream->signal)) { in update_stream_signal()
54 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
55 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && in update_stream_signal()
56 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) in update_stream_signal()
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Ddc_state.c42 dc->ctx->logger
49 if (state->phantom_stream_count >= MAX_PHANTOM_PIPES) in dc_state_track_phantom_stream()
52 state->phantom_streams[state->phantom_stream_count++] = phantom_stream; in dc_state_track_phantom_stream()
63 for (i = 0; i < state->phantom_stream_count; i++) { in dc_state_untrack_phantom_stream()
64 if (state->phantom_streams[i] == phantom_stream) { in dc_state_untrack_phantom_stream()
65 state->phantom_streams[i] = NULL; in dc_state_untrack_phantom_stream()
76 state->phantom_stream_count--; in dc_state_untrack_phantom_stream()
77 for (; i < state->phantom_stream_count; i++) in dc_state_untrack_phantom_stream()
78 state->phantom_streams[i] = state->phantom_streams[i + 1]; in dc_state_untrack_phantom_stream()
87 for (i = 0; i < state->phantom_stream_count; i++) { in dc_state_is_phantom_stream_tracked()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
Ddcn10_hwseq.h2 * Copyright 2016-2020 Advanced Micro Devices, Inc.
32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
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Ddcn10_hwseq.c67 hws->ctx
69 hws->regs->reg
73 hws->shifts->field_name, hws->masks->field_name
88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
97 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
107 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
108 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
109 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
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/linux-6.12.1/drivers/md/
Ddm-delay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2007 Red Hat GmbH
18 #include <linux/device-mapper.h>
55 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
57 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
60 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
62 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
65 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
67 return !!dc->worker; in delay_is_fast()
75 n = bio->bi_next; in flush_bios()
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/linux-6.12.1/drivers/tty/
Dnozomi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
132 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
133 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
157 CTRL_ERROR = -1,
167 PORT_ERROR = -1,
176 * else A-channels must always be used.
246 * else A-channels must always be used.
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/
DMakefile24 # Makefile for the 'utils' sub-component of DAL.
33 frame_warn_flag := -Wframe-larger-than=3072
35 frame_warn_flag := -Wframe-larger-than=2048
39 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
40 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
41 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
42 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
43 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
44 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
45 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
Ddcn31_hwseq.c57 hws->ctx
59 hws->regs->reg
61 dc->ctx->logger
66 hws->shifts->field_name, hws->masks->field_name
68 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
70 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
73 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
81 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
86 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
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/linux-6.12.1/drivers/md/bcache/
Dwriteback.c1 // SPDX-License-Identifier: GPL-2.0
3 * background writeback - scan btree for dirty data and write it to the backing
22 if (c->gc_after_writeback != (BCH_ENABLE_AUTO_GC) || in update_gc_after_writeback()
23 c->gc_stats.in_use < BCH_AUTO_GC_DIRTY_THRESHOLD) in update_gc_after_writeback()
26 c->gc_after_writeback |= BCH_DO_AUTO_GC; in update_gc_after_writeback()
30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
36 * flash-only devices in __calc_target_rate()
38 uint64_t cache_sectors = c->nbuckets * c->cache->sb.bucket_size - in __calc_target_rate()
39 atomic_long_read(&c->flash_dev_dirty_sectors); in __calc_target_rate()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
Ddcn35_hwseq.c1 /* SPDX-License-Identifier: MIT */
65 hws->ctx
67 hws->regs->reg
74 hws->shifts->field_name, hws->masks->field_name
76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
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Ddcn35_hwseq.h1 /* SPDX-License-Identifier: MIT */
32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *dc);
60 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
61 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
Ddcn401_hwseq.h1 // SPDX-License-Identifier: MIT
9 #include "dc.h"
14 struct dc;
36 void dcn401_init_hw(struct dc *dc);
40 bool dcn401_set_output_transfer_func(struct dc *dc,
43 void dcn401_trigger_3dlut_dma_load(struct dc *dc,
50 struct dc *dc);
52 void dcn401_populate_mcm_luts(struct dc *dc,
60 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
62 struct ips_ono_region_state dcn401_read_ono_state(struct dc *dc,
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Ddcn401_hwseq.c1 // SPDX-License-Identifier: MIT
40 hws->ctx
42 hws->regs->reg
44 dc->ctx->logger
49 hws->shifts->field_name, hws->masks->field_name
51 static void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
53 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
55 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
56 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
57 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn401/
Ddcn401_fpu.c1 // SPDX-License-Identifier: MIT
16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
21 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table_fpu()
22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
30 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_secon… in dcn401_build_wm_range_table_fpu()
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c28 #include "dc.h"
40 dc->ctx->logger
50 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
54 * remain as-is as it provides us with a guarantee from HW that it is correct.
70 * slow-slow corner + 10% margin with voltages aligned to FCLK.
305 input->src.is_hsplit = false; in pipe_ctx_to_e2e_pipe_params()
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || in pipe_ctx_to_e2e_pipe_params()
309 pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { in pipe_ctx_to_e2e_pipe_params()
311 input->src.hsplit_grp = pipe->pipe_idx; in pipe_ctx_to_e2e_pipe_params()
312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
Ddcn32_hwseq.c59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
77 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control() local
79 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
82 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
168 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
197 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) in dcn32_check_no_memory_request_for_cab() argument
201 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
DMakefile1 # SPDX-License-Identifier: MIT */
32 frame_warn_flag := -Wframe-larger-than=3072
34 frame_warn_flag := -Wframe-larger-than=2048
38 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2
39 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_core
40 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_mcg/
41 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_dpmm/
42 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_pmo/
43 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_standalone_libraries/
44 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/inc
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
Ddcn30_hwseq.c61 hws->ctx
63 hws->regs->reg
65 dc->ctx->logger
70 hws->shifts->field_name, hws->masks->field_name
72 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
75 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
76 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
86 for (i = 0; i < pool->pipe_count; i++) { in dcn30_log_color_state()
87 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state()
90 dpp->funcs->dpp_read_state(dpp, &s); in dcn30_log_color_state()
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/linux-6.12.1/drivers/gpu/drm/tegra/
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
32 #include "dc.h"
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
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/linux-6.12.1/drivers/scsi/esas2r/
Desas2r_disc.c5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
8 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
85 struct esas2r_sas_nvram *nvr = a->nvram; in esas2r_disc_initialize()
89 clear_bit(AF_DISC_IN_PROG, &a->flags); in esas2r_disc_initialize()
90 clear_bit(AF2_DEV_SCAN, &a->flags2); in esas2r_disc_initialize()
91 clear_bit(AF2_DEV_CNT_OK, &a->flags2); in esas2r_disc_initialize()
93 a->disc_start_time = jiffies_to_msecs(jiffies); in esas2r_disc_initialize()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
Ddcn20_hwseq.c66 hws->ctx
68 hws->regs->reg
72 hws->shifts->field_name, hws->masks->field_name
74 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
87 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
88 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state()
91 dpp->funcs->dpp_read_state(dpp, &s); in dcn20_log_color_state()
92 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn20_log_color_state()
[all …]
/linux-6.12.1/drivers/clk/mvebu/
Ddove-divider.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
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