Home
last modified time | relevance | path

Searched +full:cortex +full:- +full:m3 (Results 1 – 25 of 34) sorted by relevance

12

/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dwkup_m3_rproc.txt1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
17 --------------------
18 - compatible: Should be one of,
19 "ti,am3352-wkup-m3" for AM33xx SoCs
20 "ti,am4372-wkup-m3" for AM43xx SoCs
21 - reg: Should contain the address ranges for the two internal
[all …]
Dqcom,rpm-proc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
12 - Stephan Gerhold <stephan@gerhold.net>
17 +--------------------------------------------+
18 | RPM subsystem (qcom,rpm-proc) |
20 reset | +---------------+ +-----+ +-----+ |
[all …]
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/linux-6.12.1/arch/arm/mm/
Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
15 #include "proc-macros.S"
32 * - loc - location to jump to for soft reset
105 * This should be able to cover all ARMv7-M cores.
141 ldmia sp, {r0-r3, r12}
145 @ Special-purpose control register
151 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
153 teq r8, #0 @ re-evalutae condition
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/renesas/
Drenesas.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas SH-Mobile, R-Mobile, and R-Car Platform
10 - Geert Uytterhoeven <geert+renesas@glider.be>
17 - description: Emma Mobile EV2
19 - enum:
20 - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual
21 - const: renesas,emev2
23 - description: RZ/A1H (R7S72100)
[all …]
/linux-6.12.1/drivers/soc/ti/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 Packets are queued/de-queued by writing/reading descriptor address
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
48 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
50 to communicate and use the Wakeup M3 for PM features like suspend
75 tristate "TI PRU-ICSS Subsystem Platform drivers"
79 TI PRU-ICSS Subsystem platform specific support.
/linux-6.12.1/Documentation/devicetree/bindings/soc/ti/
Dwkup-m3-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Wakeup M3 IPC device
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
15 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
[all …]
/linux-6.12.1/arch/arm/mach-versatile/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mailbox/
Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
2 the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
18 - #mbox-cells: only one to specify the mailbox channel number.
24 compatible = "apm,xgene-slimpro-mbox";
26 #mbox-cells = <1>;
/linux-6.12.1/Documentation/staging/
Drpmsg.rst17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
21 and each of the other three cores (two M3 cores and a DSP) is running
25 hardware accelerators, and therefore are often used to offload CPU-intensive
28 These remote processors could also be used to control latency-sensitive
34 hardware accessible only by the remote processor, reserving kernel-controlled
37 Rpmsg is a virtio-based messaging bus that allows kernel drivers to communicate
60 a unique rpmsg local address (a 32-bit integer). This way when inbound messages
84 -ERESTARTSYS is returned.
[all …]
Dremoteproc.rst10 of operating system, whether it's Linux or any other flavor of real-time OS.
12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
13 In a typical configuration, the dual cortex-A9 is running Linux in a SMP
14 configuration, and each of the other three cores (two M3 cores and a DSP)
22 platform-specific remoteproc drivers only need to provide a few low-level
24 (for more information about the virtio-based rpmsg bus and its drivers,
118 name of this remote processor, platform-specific ops handlers,
154 This is called by the platform-specific rproc implementation, whenever
180 Returns 0 on success and -EINVAL if @rproc isn't valid.
190 non-remoteproc driver. This function can be called from atomic/interrupt
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/linux-6.12.1/Documentation/locking/
Dhwspinlock.rst12 For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
14 is usually running Linux and the slave processors, the M3 and the DSP,
17 A generic hwspinlock framework allows platform-independent drivers to use
22 This is necessary, for example, for Inter-processor communications:
23 on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the
24 remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink).
26 To achieve fast message-based communications, a minimal kernel support
35 A common hwspinlock interface makes it possible to have generic, platform-
67 Retrieve the global lock id for an OF phandle-based specific lock.
72 The function returns a lock id number on success, -EPROBE_DEFER if
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-nvic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
9 * ARMv7-M CPUs (Cortex-M3/M4)
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; in nvic_handle_irq()
85 return -ENOMEM; in nvic_of_init()
98 return -ENOMEM; in nvic_of_init()
115 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
116 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
117 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
[all …]
/linux-6.12.1/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
159 The ARM series is a line of low-power-consumption RISC chip designs
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
[all …]
/linux-6.12.1/drivers/firmware/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
19 provides a mechanism for inter-processor communication between SCP
62 bool "Add firmware-provided memory map to sysfs" if EXPERT
65 Add the firmware-provided (unmodified) memory map to /sys/firmware/memmap.
69 See also Documentation/ABI/testing/sysfs-firmware-memmap.
78 DMI-based module auto-loading.
193 bootloader or kernel can show basic video-output during boot for
194 user-guidance and debugging. Historically, x86 used the VESA BIOS
195 Extensions and EFI-framebuffers for this, which are mostly limited
[all …]
/linux-6.12.1/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
37 will be discovered and possibly managed at probe-time.
71 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
88 This driver provides support for inter-processor communication
176 module will be called mailbox-mpfs.
185 providing an interface for invoking the inter-process communication
198 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
201 An implementation of the APM X-Gene Interprocessor Communication
202 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
57 u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
64 writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
70 writel_relaxed(BIT(pin), ic->base + reg); in lpc18xx_gpio_pin_ic_set()
75 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_mask()
78 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
81 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
85 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
88 raw_spin_unlock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
95 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_unmask()
[all …]
/linux-6.12.1/drivers/ssb/
Dscan.c5 * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
6 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
78 return "SATA XOR-DMA"; in ssb_core_name()
82 return "PCI-E"; in ssb_core_name()
94 return "ARM Cortex M3"; in ssb_core_name()
103 switch (pci_dev->device) { in pcidev_to_chipid()
128 dev_err(&pci_dev->dev, "PCI-ID not in fallback list\n"); in pcidev_to_chipid()
165 switch (bus->bustype) { in scan_read32()
174 offset -= 0x800; in scan_read32()
177 lo = readw(bus->mmio + offset); in scan_read32()
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/linux-6.12.1/drivers/net/pcs/
Dpcs-rzn1-miic.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pcs-rzn1-miic.h>
17 #include <dt-bindings/net/pcs-rzn1-miic.h>
52 #define MIIC_MODCTRL_CONF_NONE -1
55 * struct modctrl_match - Matching table entry for convctrl configuration
59 * then index 1 - 5 are CONV1 - CONV5.
122 * struct miic - MII converter structure
125 * @lock: Lock used for read-modify-write access
134 * struct miic_port - Per port MII converter struct
154 writel(value, miic->base + offset); in miic_reg_writel()
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Dam33xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
30 d-can0 = &dcan0;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc18xx.dtsi9 * Released under the terms of 3-clause BSD License
14 #include "../../armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-m3";
40 compatible = "fixed-clock";
[all …]
/linux-6.12.1/drivers/clk/mvebu/
Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
201 .parent_names = (const char *[]){ "TBG-A-P", \
202 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
211 .parent_names = (const char *[]){ "TBG-A-P", \
[all …]

12