Searched full:cppi (Results 1 – 23 of 23) sorted by relevance
16 /* CPPI RX/TX state RAM */40 /* hw_options bits in CPPI buffer descriptors */43 #define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */53 /* CPPI data structure definitions */70 struct cppi;72 /* CPPI Channel Control structure */77 struct cppi *controller;93 void __iomem *state_ram; /* CPPI state */108 /* CPPI DMA controller object */109 struct cppi { struct[all …]
153 bool 'TI CPPI 4.1'
204 * This assumes the separate CPPI engine is responding to DMA requests346 * OK since the transfer dma glue (between CPPI and in txstate()347 * Mentor fifos) just tells CPPI it could start. Data in txstate()447 * SHOULD NOT HAPPEN... has with CPPI though, after in musb_g_tx()560 /* NOTE: CPPI won't actually stop advancing the DMA in rxstate()572 * the cppi engine will be ready to take it as soon in rxstate()
598 /* delay to drain to cppi dma pipeline for isoch */ in cppi41_dma_channel_abort()605 /* wait to drain cppi dma pipe line */ in cppi41_dma_channel_abort()
36 * - DMA (CPPI) ... partially behaves, not currently recommended111 * CPPI enabled to see the issue when aborting the tx channel. in musb_h_tx_flush_fifo()1214 /* with CPPI, DMA sometimes triggers "extra" irqs */ in musb_host_tx()1290 /* second cppi case */ in musb_host_tx()
245 /* Acknowledge and handle non-CPPI interrupts */ in da8xx_musb_interrupt()
7 tristate "Texas Instruments CPPI 4.1 DMA support"11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
1255 MODULE_DESCRIPTION("Texas Instruments CPPI 4.1 DMA support");
33 - reg: offset and length of the following register spaces: CPPI DMA Controller,34 CPPI DMA Scheduler, Queue Manager
58 CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
26 obj-$(CONFIG_TI_K3_CPPI_DESC_POOL) += k3-cppi-desc-pool.o
15 #include "k3-cppi-desc-pool.h"
110 Communications Port Programming Interface (CPPI) port (port 0).
5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine192 /* CPPI bit positions */200 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
231 * if memory size > CPPI internal RAM size (desc_mem_size) in cpdma_desc_pool_create()
41 #include "k3-cppi-desc-pool.h"155 /* CPPI streaming packet interface */
64 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
3532 * NU cppi port 0 tx pkt streaming interface has (n-1)*8 egress threads in set_gbenu_ethss_priv()
38 CPPI/QMSS Low Level Driver document (docs/CPPI_QMSS_LLD_SDS.pdf) at
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
23 #include "../k3-cppi-desc-pool.h"
26 #include "../k3-cppi-desc-pool.h"
37 #include "../k3-cppi-desc-pool.h"