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Searched full:clk_top_xfi_phy_0_xtal_sel (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dmediatek,mt7988-xfi-tphy.yaml72 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt7988-clk.h99 #define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt7988-topckgen.c199 MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,