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Searched full:clk_top_vdec_sel (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-subdev-decoder.yaml231 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
237 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
257 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
263 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
Dmediatek,vcodec-decoder.yaml177 <&topckgen CLK_TOP_VDEC_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
/linux-6.12.1/include/dt-bindings/clock/
Dmt8135-clk.h93 #define CLK_TOP_VDEC_SEL 82 macro
Dmediatek,mt6795-clk.h95 #define CLK_TOP_VDEC_SEL 84 macro
Dmt8173-clk.h97 #define CLK_TOP_VDEC_SEL 87 macro
Dmt2712-clk.h134 #define CLK_TOP_VDEC_SEL 103 macro
Dmt2701-clk.h93 #define CLK_TOP_VDEC_SEL 82 macro
Dmt8192-clk.h64 #define CLK_TOP_VDEC_SEL 52 macro
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8192.dtsi637 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1719 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1725 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1745 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1751 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
Dmt8173.dtsi1410 <&topckgen CLK_TOP_VDEC_SEL>,
1425 <&topckgen CLK_TOP_VDEC_SEL>,
Dmt2712e.dtsi290 <&topckgen CLK_TOP_VDEC_SEL>;
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c461 TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x50, 8, 4, 15, 0),
Dclk-mt8135.c382 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
Dclk-mt8173-topckgen.c540 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
Dclk-mt2712.c651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15),
Dclk-mt2701.c498 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
Dclk-mt8192.c669 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",