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Searched full:clk_top_spislv_sel (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dmediatek,spi-slave-mt27xx.yaml56 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
/linux-6.12.1/include/dt-bindings/clock/
Dmt2712-clk.h188 #define CLK_TOP_SPISLV_SEL 157 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt2712.c736 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, 31),
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt2712e.dtsi321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;