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/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt6795-clk.h46 #define CLK_TOP_MSDCPLL_D2 35 macro
Dmt6797-clk.h102 #define CLK_TOP_MSDCPLL_D2 92 macro
Dmt8173-clk.h48 #define CLK_TOP_MSDCPLL_D2 38 macro
Dmt6765-clk.h75 #define CLK_TOP_MSDCPLL_D2 40 macro
Dmediatek,mt8365-clk.h64 #define CLK_TOP_MSDCPLL_D2 54 macro
Dmt2712-clk.h111 #define CLK_TOP_MSDCPLL_D2 80 macro
Dmt8183-clk.h122 #define CLK_TOP_MSDCPLL_D2 86 macro
Dmt6779-clk.h97 #define CLK_TOP_MSDCPLL_D2 87 macro
Dmt8186-clk.h130 #define CLK_TOP_MSDCPLL_D2 111 macro
Dmt2701-clk.h48 #define CLK_TOP_MSDCPLL_D2 38 macro
Dmt8192-clk.h137 #define CLK_TOP_MSDCPLL_D2 125 macro
Dmediatek,mt8188-clk.h168 #define CLK_TOP_MSDCPLL_D2 157 macro
Dmt8195-clk.h203 #define CLK_TOP_MSDCPLL_D2 191 macro
/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml334 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c399 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
Dclk-mt8173-topckgen.c478 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
Dclk-mt8186-topckgen.c65 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
Dclk-mt6797.c82 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
Dclk-mt8365.c85 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
Dclk-mt8183.c95 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
Dclk-mt2712.c118 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
Dclk-mt2701.c97 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
Dclk-mt6765.c125 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8183-kukui.dtsi387 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
Dmt8173-elm.dtsi395 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;

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