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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dmt8186-afe-pcm.yaml143 <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2
Dmediatek,mt8188-afe.yaml198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
/linux-6.12.1/include/dt-bindings/clock/
Dmt8516-clk.h198 #define CLK_TOP_APLL12_CK_DIV2 166 macro
Dmediatek,mt8365-clk.h124 #define CLK_TOP_APLL12_CK_DIV2 114 macro
Dmt8186-clk.h152 #define CLK_TOP_APLL12_CK_DIV2 133 macro
Dmediatek,mt8188-clk.h192 #define CLK_TOP_APLL12_CK_DIV2 181 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8516.c483 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
Dclk-mt8186-topckgen.c676 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
Dclk-mt8167.c672 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
Dclk-mt8365.c557 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
Dclk-mt8188-topckgen.c1184 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8186.dtsi1518 <&topckgen CLK_TOP_APLL12_CK_DIV2>,