Home
last modified time | relevance | path

Searched full:clk_top_a1sys_hp_sel (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt7622-clk.h82 #define CLK_TOP_A1SYS_HP_SEL 70 macro
Dmt2712-clk.h172 #define CLK_TOP_A1SYS_HP_SEL 141 macro
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dmt8195-afe-pcm.yaml168 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt7622.c420 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
Dclk-mt2712.c713 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi689 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
Dmt2712e.dtsi289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,