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/linux-6.12.1/Documentation/devicetree/bindings/pwm/
Dmediatek,mt2712-pwm.yaml89 <&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>;
/linux-6.12.1/include/dt-bindings/clock/
Dmt8135-clk.h162 #define CLK_PERI_PWM7 24 macro
Dmediatek,mt6795-clk.h183 #define CLK_PERI_PWM7 8 macro
Dmt8173-clk.h202 #define CLK_PERI_PWM7 9 macro
Dmt2712-clk.h248 #define CLK_PERI_PWM7 9 macro
Dmt2701-clk.h230 #define CLK_PERI_PWM7 9 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8173-pericfg.c59 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
Dclk-mt6795-pericfg.c48 GATE_PERI(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
Dclk-mt8135.c473 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
Dclk-mt2712.c894 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9),
Dclk-mt2701.c847 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt6795.dtsi612 <&pericfg CLK_PERI_PWM7>;
Dmt2712e.dtsi491 <&pericfg CLK_PERI_PWM7>;