Home
last modified time | relevance | path

Searched full:clk_pciephy0_ref (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dphy-rockchip-naneng-combphy.yaml132 clocks = <&pmucru CLK_PCIEPHY0_REF>,
136 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi258 clocks = <&pmucru CLK_PCIEPHY0_REF>,
262 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
/linux-6.12.1/include/dt-bindings/clock/
Drk3568-cru.h44 #define CLK_PCIEPHY0_REF 31 macro
/linux-6.12.1/drivers/clk/rockchip/
Dclk-rk3568.c1559 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,