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/linux-6.12.1/include/dt-bindings/clock/
Dmt7986-clk.h19 #define CLK_APMIXED_APLL2 7 macro
Dmt8516-clk.h18 #define CLK_APMIXED_APLL2 5 macro
Dmediatek,mt7981-clk.h195 #define CLK_APMIXED_APLL2 7 macro
Dmediatek,mt6795-clk.h151 #define CLK_APMIXED_APLL2 10 macro
Dmediatek,mt7988-clk.h16 #define CLK_APMIXED_APLL2 3 macro
Dmt6797-clk.h117 #define CLK_APMIXED_APLL2 10 macro
Dmt8173-clk.h167 #define CLK_APMIXED_APLL2 12 macro
Dmediatek,mt8365-clk.h238 #define CLK_APMIXED_APLL2 7 macro
Dmt2712-clk.h17 #define CLK_APMIXED_APLL2 5 macro
Dmt8183-clk.h21 #define CLK_APMIXED_APLL2 10 macro
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dmediatek,mt7986-afe.yaml156 <&apmixedsys CLK_APMIXED_APLL2>,
Dmt8186-afe-pcm.yaml131 <&apmixedsys 13>, //CLK_APMIXED_APLL2
Dmediatek,mt8188-afe.yaml195 <&apmixedsys 10>, //CLK_APMIXED_APLL2
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt7986-apmixed.c57 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
Dclk-mt8516-apmixedsys.c70 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
Dclk-mt7981-apmixed.c59 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
Dclk-mt7988-apmixed.c54 PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
Dclk-mt8167-apmixedsys.c69 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
Dclk-mt2712-apmixedsys.c90 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
Dclk-mt8188-apmixedsys.c81 PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
Dclk-mt8365-apmixedsys.c97 PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32,
Dclk-mt8186-apmixedsys.c77 PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
Dclk-mt6795-apmixedsys.c60 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
Dclk-mt8192-apmixedsys.c91 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000,
Dclk-mt8173-apmixedsys.c77 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),

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