| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-spmi-pmic-div.c | 24 struct clkdiv { struct
33 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) in to_clkdiv() argument
35 return container_of(hw, struct clkdiv, hw); in to_clkdiv()
51 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
61 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
65 unsigned int ns = clkdiv->cxo_period_ns; in __spmi_pmic_clkdiv_set_enable_state()
68 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, in __spmi_pmic_clkdiv_set_enable_state()
81 static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable) in spmi_pmic_clkdiv_set_enable_state() argument
85 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); in spmi_pmic_clkdiv_set_enable_state()
[all …]
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| /linux-6.12.1/drivers/spi/ |
| D | spi-cavium.h | 46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
142 uint64_t clkdiv:13;
150 uint64_t clkdiv:13; member
180 uint64_t clkdiv:13;
187 uint64_t clkdiv:13; member
217 uint64_t clkdiv:13;
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| D | spi-cavium.c | 36 unsigned int clkdiv; in octeon_spi_do_transfer() local
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
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| D | spi-pci1xxxx.c | 136 u8 clkdiv; member
385 u8 clkdiv, u32 len) in pci1xxxx_spi_setup() argument
397 regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv); in pci1xxxx_spi_setup()
422 u8 clkdiv; in pci1xxxx_spi_transfer_with_io() local
426 clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz); in pci1xxxx_spi_transfer_with_io()
450 pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len); in pci1xxxx_spi_transfer_with_io()
495 p->clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz); in pci1xxxx_spi_transfer_with_dma()
505 pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); in pci1xxxx_spi_transfer_with_dma()
616 p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); in pci1xxxx_spi_setup_next_dma_transfer()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,spmi-clkdiv.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
20 const: qcom,spmi-clkdiv
38 description: Number of CLKDIV peripherals.
57 compatible = "qcom,spmi-clkdiv";
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| D | baikal,bt1-ccu-div.yaml | 58 CLKDIV--|--| | | |-|->CLKLOUT
68 accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
72 figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
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| D | renesas,emev2-smu.yaml | 49 const: renesas,emev2-smu-clkdiv
129 compatible = "renesas,emev2-smu-clkdiv";
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| /linux-6.12.1/drivers/hwtracing/intel_th/ |
| D | pti.c | 27 unsigned int clkdiv; member
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
131 pti->clkdiv = val; in clock_divider_store()
159 ctl |= pti->clkdiv << __ffs(PTI_CLKDIV); in intel_th_pti_activate()
183 pti->clkdiv = (ctl & PTI_CLKDIV) >> __ffs(PTI_CLKDIV); in read_hw_config()
188 if (!pti->clkdiv) in read_hw_config()
189 pti->clkdiv = 1; in read_hw_config()
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| /linux-6.12.1/arch/arm/boot/dts/renesas/ |
| D | emev2.dtsi | 72 compatible = "renesas,emev2-smu-clkdiv";
84 compatible = "renesas,emev2-smu-clkdiv";
103 compatible = "renesas,emev2-smu-clkdiv";
109 compatible = "renesas,emev2-smu-clkdiv";
115 compatible = "renesas,emev2-smu-clkdiv";
121 compatible = "renesas,emev2-smu-clkdiv";
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| /linux-6.12.1/drivers/pwm/ |
| D | pwm-tiehrpwm.c | 152 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
154 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
160 * CLKDIVIDER = (1), if clkdiv == 0 *OR* in set_prescale_div()
161 * (2 * clkdiv), if clkdiv != 0 in set_prescale_div()
167 *prescale_div = (1 << clkdiv) * in set_prescale_div()
170 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
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| D | pwm-mediatek.c | 122 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, in pwm_mediatek_config() local
143 clkdiv++; in pwm_mediatek_config()
148 if (clkdiv > PWM_CLK_DIV_MAX) { in pwm_mediatek_config()
164 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
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| /linux-6.12.1/drivers/w1/masters/ |
| D | mxc_w1.c | 95 unsigned int clkdiv; in mxc_w1_probe() local
116 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); in mxc_w1_probe()
117 clkrate /= clkdiv; in mxc_w1_probe()
132 writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); in mxc_w1_probe()
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| /linux-6.12.1/sound/soc/adi/ |
| D | axi-spdif.c | 80 unsigned int clkdiv, stat; in axi_spdif_hw_params() local
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
99 clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; in axi_spdif_hw_params()
103 AXI_SPDIF_CTRL_CLKDIV_MASK, clkdiv); in axi_spdif_hw_params()
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| /linux-6.12.1/sound/soc/codecs/ |
| D | adau1701.c | 299 static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv, in adau1701_reset() argument
308 if (clkdiv != ADAU1707_CLKDIV_UNSET && adau1701->gpio_pll_mode) { in adau1701_reset()
309 switch (clkdiv) { in adau1701_reset()
333 adau1701->pll_clkdiv = clkdiv; in adau1701_reset()
348 if (clkdiv != ADAU1707_CLKDIV_UNSET) { in adau1701_reset()
440 unsigned int clkdiv = adau1701->sysclk / params_rate(params); in adau1701_hw_params() local
449 if (clkdiv != adau1701->pll_clkdiv) { in adau1701_hw_params()
450 ret = adau1701_reset(component, clkdiv, params_rate(params)); in adau1701_hw_params()
823 of_property_read_u32(dev->of_node, "adi,pll-clkdiv", in adau1701_i2c_probe()
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| /linux-6.12.1/drivers/iio/adc/ |
| D | lpc18xx_adc.c | 133 unsigned int clkdiv; in lpc18xx_adc_probe() local
176 clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET); in lpc18xx_adc_probe()
178 adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) | in lpc18xx_adc_probe()
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| /linux-6.12.1/drivers/gpu/drm/exynos/ |
| D | exynos7_drm_decon.c | 144 u32 clkdiv; in decon_calc_clkdiv() local
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
149 return (clkdiv < 0x100) ? clkdiv : 0xff; in decon_calc_clkdiv()
156 u32 val, clkdiv; in decon_commit() local
205 clkdiv = decon_calc_clkdiv(ctx, mode); in decon_commit()
206 if (clkdiv > 1) { in decon_commit()
207 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); in decon_commit()
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| D | exynos_drm_fimd.c | 194 u32 clkdiv; member
420 u32 clkdiv; in fimd_atomic_check() local
446 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); in fimd_atomic_check()
447 if (clkdiv >= 0x200) { in fimd_atomic_check()
453 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; in fimd_atomic_check()
588 if (ctx->clkdiv > 1) in fimd_commit()
589 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; in fimd_commit()
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| /linux-6.12.1/drivers/gpu/drm/tilcdc/ |
| D | tilcdc_crtc.c | 208 unsigned int clkdiv; in tilcdc_crtc_set_clk() local
211 clkdiv = 2; /* first try using a standard divider of 2 */ in tilcdc_crtc_set_clk()
216 ret = clk_set_rate(priv->clk, pclk_rate * clkdiv); in tilcdc_crtc_set_clk()
218 real_pclk_rate = clk_rate / clkdiv; in tilcdc_crtc_set_clk()
234 clkdiv = DIV_ROUND_CLOSEST(clk_rate, pclk_rate); in tilcdc_crtc_set_clk()
243 real_pclk_rate = clk_rate / clkdiv; in tilcdc_crtc_set_clk()
255 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); in tilcdc_crtc_set_clk()
258 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | in tilcdc_crtc_set_clk()
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| /linux-6.12.1/drivers/mmc/host/ |
| D | sunplus-mmc.c | 233 unsigned int clkdiv; in spmmc_set_bus_clk() local
243 clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1; in spmmc_set_bus_clk()
244 if (clkdiv > 0xfff) in spmmc_set_bus_clk()
245 clkdiv = 0xfff; in spmmc_set_bus_clk()
247 value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv); in spmmc_set_bus_clk()
254 int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG)); in spmmc_set_bus_timing() local
255 int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7; in spmmc_set_bus_timing()
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| D | sh_mmcif.c | 240 u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */
484 unsigned int clkdiv; in sh_mmcif_clock_control() local
496 clkdiv = 0; in sh_mmcif_clock_control()
515 clkdiv = i; in sh_mmcif_clock_control()
521 (best_freq >> (clkdiv + 1)), clk, best_freq, clkdiv); in sh_mmcif_clock_control()
524 clkdiv = clkdiv << 16; in sh_mmcif_clock_control()
526 clkdiv = CLK_SUP_PCLK; in sh_mmcif_clock_control()
528 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; in sh_mmcif_clock_control()
531 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); in sh_mmcif_clock_control()
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| D | atmel-mci.c | 552 seq_printf(s, "{CLKDIV,CLKODD}=%u\n", in atmci_regs_show()
556 seq_printf(s, "CLKDIV=%u\n", in atmci_regs_show()
1428 int clkdiv; in atmci_set_ios() local
1451 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; in atmci_set_ios()
1452 if (clkdiv < 0) { in atmci_set_ios()
1456 clkdiv = 0; in atmci_set_ios()
1457 } else if (clkdiv > 511) { in atmci_set_ios()
1461 clkdiv = 511; in atmci_set_ios()
1463 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) in atmci_set_ios()
1464 | ATMCI_MR_CLKODD(clkdiv & 1); in atmci_set_ios()
[all …]
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| /linux-6.12.1/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_common.c | 170 * @clkdiv: clock divider value to put into CDM PSC register.
172 int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv) in mpc52xx_set_psc_clkdiv() argument
183 mclken_div = 0x8000 | (clkdiv & 0x1FF); in mpc52xx_set_psc_clkdiv()
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| /linux-6.12.1/Documentation/devicetree/bindings/iio/frequency/ |
| D | adi,adf4350.yaml | 122 Clock divider value used when adi,12bit-clkdiv-mode != 0
128 Valid values for the clkdiv mode are:
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| /linux-6.12.1/arch/mips/lantiq/falcon/ |
| D | reset.c | 48 (0x2 << 24) | /* CLKDIV */ in machine_restart()
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| /linux-6.12.1/drivers/i2c/busses/ |
| D | i2c-ibm_iic.h | 33 u8 clkdiv; member
|