/linux-6.12.1/drivers/clocksource/ |
D | timer-sp804.c | 259 struct clk *clk1, *clk2; in sp804_of_init() local 284 clk2 = of_clk_get(np, 1); in sp804_of_init() 285 if (IS_ERR(clk2)) { in sp804_of_init() 287 (int)PTR_ERR(clk2)); in sp804_of_init() 288 clk2 = NULL; in sp804_of_init() 291 clk2 = clk1; in sp804_of_init() 302 ret = sp804_clockevents_init(timer2_base, irq, clk2, name); in sp804_of_init() 317 name, clk2, 1); in sp804_of_init()
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/linux-6.12.1/drivers/clk/ti/ |
D | clk-33xx.c | 272 struct clk *clk1, *clk2; in am33xx_dt_clk_init() local 293 clk2 = clk_get_sys(NULL, "timer3_fck"); in am33xx_dt_clk_init() 294 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init() 296 clk2 = clk_get_sys(NULL, "timer6_fck"); in am33xx_dt_clk_init() 297 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init() 306 clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); in am33xx_dt_clk_init() 307 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
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D | clk-43xx.c | 275 struct clk *clk1, *clk2; in am43xx_dt_clk_init() local 297 clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); in am43xx_dt_clk_init() 298 clk_set_parent(clk1, clk2); in am43xx_dt_clk_init()
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/linux-6.12.1/drivers/phy/allwinner/ |
D | phy-sun4i-usb.c | 125 struct clk *clk2; member 268 ret = clk_prepare_enable(phy->clk2); in sun4i_usb_phy_init() 276 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init() 288 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init() 297 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init() 306 ret = clk_prepare_enable(phy2->clk2); in sun4i_usb_phy_init() 311 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init() 322 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init() 397 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_exit() 818 phy->clk2 = devm_clk_get(dev, name); in sun4i_usb_phy_probe() [all …]
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/linux-6.12.1/sound/soc/codecs/ |
D | pcm3060.h | 20 /* ADC and DAC can be clocked from separate or same sources CLK1 and CLK2 */ 21 #define PCM3060_CLK_DEF 0 /* default: CLK1->ADC, CLK2->DAC */
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/linux-6.12.1/Documentation/devicetree/bindings/iio/frequency/ |
D | adi,adf4377.yaml | 53 clk2-enable-gpios: 85 clk2-enable-gpios: false
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/linux-6.12.1/Documentation/devicetree/bindings/soc/tegra/ |
D | nvidia,tegra20-pmc.yaml | 273 hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, 281 hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 341 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 361 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
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/linux-6.12.1/Documentation/devicetree/bindings/arm/tegra/ |
D | nvidia,tegra186-pmc.yaml | 105 csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, 113 csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
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/linux-6.12.1/sound/soc/qcom/ |
D | lpass-apq8016.c | 275 "mi2s-osr-clk2", 281 "mi2s-bit-clk2",
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/linux-6.12.1/drivers/video/fbdev/matrox/ |
D | matroxfb_Ti3026.c | 172 #define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/ 173 #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */ 174 #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
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/linux-6.12.1/include/dt-bindings/clock/ |
D | intel,lgm-clk.h | 134 /* Gate CLK2 */
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/linux-6.12.1/drivers/clk/renesas/ |
D | r9a08g045-cpg.c | 53 #define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) argument
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D | rzv2h-cpg.c | 137 unsigned int clk1, clk2; in rzv2h_cpg_pll_clk_recalc_rate() local 144 clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf)); in rzv2h_cpg_pll_clk_recalc_rate() 147 16 + SDIV(clk2)); in rzv2h_cpg_pll_clk_recalc_rate()
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/linux-6.12.1/arch/powerpc/platforms/8xx/ |
D | mpc86xads_setup.c | 48 {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
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D | tqm8xx_setup.c | 56 {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
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D | ep88xc.c | 76 {0, 6, CPM_PIN_INPUT}, /* CLK2 */
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/linux-6.12.1/drivers/clk/rockchip/ |
D | clk-rk3188.c | 823 struct clk *clk1, *clk2; in rk3188a_clk_init() local 845 clk2 = __clk_lookup("gpll"); in rk3188a_clk_init() 846 if (clk1 && clk2) { in rk3188a_clk_init() 849 ret = clk_set_parent(clk1, clk2); in rk3188a_clk_init()
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/linux-6.12.1/Documentation/devicetree/bindings/sound/ |
D | qcom,lpass-cpu.yaml | 151 - const: mi2s-bit-clk2
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ |
D | silabs,si5351.yaml | 257 * Overwrite CLK2 configuration with:
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/linux-6.12.1/drivers/clk/sunxi-ng/ |
D | ccu-suniv-f1c100s.c | 294 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2", 297 static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
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/linux-6.12.1/arch/arm64/boot/dts/renesas/ |
D | r8a779h0-gray-hawk-single.dts | 390 scif_clk2_pins: scif-clk2 {
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/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/ |
D | lpc4350-hitex-eval.dts | 230 pins = "clk0", "clk1", "clk2", "clk3";
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/linux-6.12.1/drivers/video/fbdev/ |
D | pxa168fb.c | 234 * clk2 = clk_in / integer_divider 235 * clk_out = clk2 * (1 - (fractional_divider >> 12))
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/linux-6.12.1/drivers/soc/tegra/ |
D | pmc.c | 3493 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3630 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3740 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3781 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3937 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3989 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
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/linux-6.12.1/arch/arm/boot/dts/nvidia/ |
D | tegra30-colibri.dtsi | 259 clk2-out-pw5 { 620 clk2-req-pcc5 {
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