/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
D | gf100.c | 279 u32 clk0, clk1 = 0; in calc_clk() local 286 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk() 287 clk0 = calc_div(clk, idx, clk0, freq, &div1D); in calc_clk() 290 if (clk0 != freq && (0x00004387 & (1 << idx))) { in calc_clk() 299 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk() 311 info->freq = clk0; in calc_clk()
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D | gk104.c | 293 u32 clk0, clk1 = 0; in calc_clk() local 300 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk() 301 clk0 = calc_div(clk, idx, clk0, freq, &div1D); in calc_clk() 304 if (clk0 != freq && (0x0000ff87 & (1 << idx))) { in calc_clk() 313 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk() 324 info->freq = clk0; in calc_clk()
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D | mcp77.c | 184 u32 clk0 = src, clk1 = src; in calc_P() local 186 if (clk0 <= target) { in calc_P() 187 clk1 = clk0 << (*div ? 1 : 0); in calc_P() 190 clk0 >>= 1; in calc_P() 193 if (target - clk0 <= clk1 - target) in calc_P() 194 return clk0; in calc_P()
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D | nv50.c | 347 u32 clk0 = src, clk1 = src; in calc_div() local 349 if (clk0 <= target) { in calc_div() 350 clk1 = clk0 << (*div ? 1 : 0); in calc_div() 353 clk0 >>= 1; in calc_div() 356 if (target - clk0 <= clk1 - target) in calc_div() 357 return clk0; in calc_div()
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/linux-6.12.1/Documentation/devicetree/bindings/sound/ |
D | qcom,lpass-cpu.yaml | 149 - const: mi2s-bit-clk0 173 - const: mi2s-bit-clk0 271 "mi2s-bit-clk0", "mi2s-bit-clk1";
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/linux-6.12.1/sound/soc/qcom/ |
D | lpass-apq8016.c | 273 "mi2s-osr-clk0", 279 "mi2s-bit-clk0",
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D | lpass-sc7180.c | 296 "mi2s-bit-clk0",
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/linux-6.12.1/drivers/clk/ti/ |
D | adpll.c | 266 char *name, struct clk *clk0, in ti_adpll_init_mux() argument 278 parents[0] = __clk_get_name(clk0); in ti_adpll_init_mux() 575 char *name, struct clk *clk0, in ti_adpll_init_clkout() argument 606 parent_names[0] = __clk_get_name(clk0); in ti_adpll_init_clkout()
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/linux-6.12.1/arch/arm/boot/dts/st/ |
D | st-pincfg.h | 68 * CLK0, CLK1 modes with non-inverted clock
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/linux-6.12.1/include/dt-bindings/clock/ |
D | intel,lgm-clk.h | 95 /* Gate CLK0 */
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/linux-6.12.1/drivers/comedi/drivers/ |
D | dmm32at.c | 51 #define DMM32AT_AUX_DI0 BIT(0) /* J3.48 - CLK0 (SRC0) */ 89 #define DMM32AT_CTRDIO_CFG_FREQ0 BIT(6) /* CLK0 1=10KHz 0=10MHz */ 93 #define DMM32AT_CTRDIO_CFG_SRC0 BIT(1) /* CLK0 is 0=FREQ0 1=J3.48 */
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/linux-6.12.1/drivers/clk/zynq/ |
D | clkc.c | 174 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, in zynq_clk_register_periph_clk() argument 197 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk() 209 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
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/linux-6.12.1/Documentation/devicetree/bindings/arm/ |
D | vexpress-config.yaml | 275 clk0 {
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
D | gpio-latch.yaml | 16 CLK0 ----------------------. ,--------.
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ |
D | silabs,si5351.yaml | 223 * Overwrite CLK0 configuration with:
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/linux-6.12.1/drivers/pinctrl/mvebu/ |
D | pinctrl-ac5.c | 205 MPP_FUNCTION(1, "ptp", "clk0"),
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/linux-6.12.1/arch/arm64/boot/dts/actions/ |
D | s900-bubblegum-96.dts | 162 "[CLK0]", /* GPIO_68, HSEC pin 15 */
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/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/ |
D | lpc4350-hitex-eval.dts | 230 pins = "clk0", "clk1", "clk2", "clk3";
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D | lpc4357-myd-lpc4357.dts | 184 pins = "clk0";
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D | lpc4357-ea4357-devkit.dts | 260 pins = "clk0", "clk1", "clk2", "clk3";
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/linux-6.12.1/drivers/gpio/ |
D | gpio-latch.c | 10 * CLK0 ----------------------. ,--------.
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/linux-6.12.1/include/video/ |
D | sstfb.h | 242 * 8 freq registers (0-7) for video clock (CLK0)
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/linux-6.12.1/drivers/pinctrl/sunxi/ |
D | pinctrl-suniv-f1c100s.c | 338 SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
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/linux-6.12.1/drivers/clk/ |
D | clk-si5351.c | 77 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7" 820 /* clk0/clk4 can only connect to its own multisync */ in _si5351_clkout_reparent()
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/linux-6.12.1/drivers/pinctrl/ |
D | pinctrl-lpc18xx.c | 416 LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS); 625 LPC18XX_PIN(clk0, PIN_CLK0),
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