Searched full:ccsr (Results 1 – 25 of 31) sorted by relevance
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| /linux-6.12.1/drivers/clk/pxa/ |
| D | clk-pxa27x.c | 71 * Get the clock frequency as reflected by CCSR and the turbo flag.
105 unsigned long ccsr = readl(clk_regs + CCSR); in pxa27x_is_ppll_disabled() local
107 return ccsr & (1 << CCCR_PPDIS_BIT); in pxa27x_is_ppll_disabled()
207 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_cpll_get_rate() local
213 l = ccsr & CCSR_L_MASK; in clk_pxa27x_cpll_get_rate()
214 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; in clk_pxa27x_cpll_get_rate()
252 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_rate() local
255 l = ccsr & CCSR_L_MASK; in clk_pxa27x_lcd_base_get_rate()
256 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); in clk_pxa27x_lcd_base_get_rate()
274 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_parent() local
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| D | clk-pxa2xx.h | 6 #define CCSR (0x000C) /* Core Clock Status Register */ macro
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | ecm.txt | 8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The E500 LAW node represents the region of CCSR space where ECM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
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| D | mcm.txt | 8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The MPX LAW node represents the region of CCSR space where MCM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
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| D | interlaken-lac.txt | 43 those LAC CCSR registers not protected in partitioned
61 Definition: Points to the non-protected LAC CCSR mapped register space
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| D | msi-pic.txt | 83 Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
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| D | pamu.txt | 32 A standard property. It represents the CCSR registers of
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| D | mpic.txt | 27 CCSR address space.
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| /linux-6.12.1/arch/powerpc/sysdev/ |
| D | fsl_rio.c | 396 static inline void fsl_rio_info(struct device *dev, u32 ccsr) in fsl_rio_info() argument
399 if (ccsr & 1) { in fsl_rio_info()
401 switch (ccsr >> 30) { in fsl_rio_info()
414 switch ((ccsr >> 27) & 7) { in fsl_rio_info()
431 if (!(ccsr & 0x80000000)) in fsl_rio_info()
433 if (!(ccsr & 0x08000000)) in fsl_rio_info()
455 u32 ccsr; in fsl_rio_setup() local
625 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20); in fsl_rio_setup()
652 fsl_rio_info(&dev->dev, ccsr); in fsl_rio_setup()
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| D | fsl_msi.h | 34 u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/ |
| D | fsl,bman.yaml | 16 This binding covers the CCSR space programming model
31 Registers region within the CCSR address space
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| D | fsl,qman.yaml | 18 CCSR space programming model
32 Registers region within the CCSR address space
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| /linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
| D | b4420si-pre.dtsi | 46 ccsr = &soc;
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| D | t102xsi-pre.dtsi | 45 ccsr = &soc;
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| D | b4860si-pre.dtsi | 46 ccsr = &soc;
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| D | p5020si-pre.dtsi | 46 ccsr = &soc;
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| D | t104xsi-pre.dtsi | 45 ccsr = &soc;
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| D | t208xsi-pre.dtsi | 45 ccsr = &soc;
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| D | p3041si-pre.dtsi | 46 ccsr = &soc;
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| D | p2041si-pre.dtsi | 46 ccsr = &soc;
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| D | p5040si-pre.dtsi | 46 ccsr = &soc;
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| D | p4080si-pre.dtsi | 46 ccsr = &soc;
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| D | t4240si-pre.dtsi | 46 ccsr = &soc;
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| /linux-6.12.1/drivers/iommu/ |
| D | fsl_pamu.h | 21 /* PAMU CCSR space */
25 /* PAMU_OFFSET to the next pamu space in ccsr */
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| /linux-6.12.1/arch/arm/mach-pxa/ |
| D | pxa2xx-regs.h | 135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ macro
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