| /linux-6.12.1/arch/mips/kernel/ |
| D | smp-bmips.c | 521 void __iomem *cbr = bmips_cbr_addr; in bmips_set_reset_vec() local
524 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); in bmips_set_reset_vec()
528 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); in bmips_set_reset_vec()
594 void __iomem __maybe_unused *cbr = bmips_cbr_addr; in bmips_cpu_setup() local
611 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
612 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
613 __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
615 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
616 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
617 __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
[all …]
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| /linux-6.12.1/tools/perf/scripts/python/ |
| D | export-to-sqlite.py | 284 do_query(query, 'CREATE TABLE cbr ('
286 'cbr integer,'
463 'cbr.id,'
466 'cbr,'
469 ' FROM cbr'
470 ' INNER JOIN samples ON samples.id = cbr.id')
524 …'CASE WHEN selected_events.name=\'cbr\' THEN (SELECT cbr FROM cbr WHERE cbr.id = samples.id) ELSE …
525 …'CASE WHEN selected_events.name=\'cbr\' THEN (SELECT mhz FROM cbr WHERE cbr.id = samples.id) ELSE …
526 …'CASE WHEN selected_events.name=\'cbr\' THEN (SELECT percent FROM cbr WHERE cbr.id = samples.id) E…
545 ' WHERE selected_events.name IN (\'cbr\',\'mwait\',\'exstop\',\'pwre\',\'pwrx\')')
[all …]
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| D | export-to-postgresql.py | 460 do_query(query, 'CREATE TABLE cbr ('
462 'cbr integer,'
625 'cbr.id,'
628 'cbr,'
631 ' FROM cbr'
632 ' INNER JOIN samples ON samples.id = cbr.id')
686 'FORMAT(\'%6s\', cbr.cbr) AS cbr,'
687 'FORMAT(\'%6s\', cbr.mhz) AS MHz,'
688 'FORMAT(\'%5s\', cbr.percent) AS percent,'
703 ' FROM cbr'
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| D | intel-pt-events.py | 153 cbr = data[0]
155 p = ((cbr * 1000 / data[2]) + 5) / 10
156 print("%3u freq: %4u MHz (%3u%%)" % (cbr, f, p), end=' ')
378 elif name == "cbr":
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| /linux-6.12.1/arch/mips/bmips/ |
| D | setup.c | 38 * CBR addr doesn't change and we can cache it.
39 * For broken SoC/Bootloader CBR addr might also be provided via DT
40 * with "brcm,bmips-cbr-reg" in the "cpus" node.
154 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
227 /* Check if DT provide a CBR address */ in device_tree_init()
228 if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) in device_tree_init()
231 /* Make sure CBR address is outside DRAM window */ in device_tree_init()
234 WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", in device_tree_init()
240 /* Since CBR is provided by DT, enable RAC flush */ in device_tree_init()
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| D | dma.c | 12 void __iomem *cbr = bmips_cbr_addr; in arch_sync_dma_for_cpu_all() local
24 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in arch_sync_dma_for_cpu_all()
25 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); in arch_sync_dma_for_cpu_all()
26 __raw_readl(cbr + BMIPS_RAC_CONFIG); in arch_sync_dma_for_cpu_all()
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| /linux-6.12.1/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.yaml | 58 brcm,bmips-cbr-reg:
59 description: Reference address of the CBR.
60 Some SoC suffer from a BUG where CBR(Core Base Register)
64 The CBR address is always the same on the SoC hence it
89 - brcm,bmips-cbr-reg
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| /linux-6.12.1/arch/mips/bcm63xx/ |
| D | setup.c | 27 * CBR addr doesn't change and we can cache it.
28 * For broken SoC/Bootloader CBR addr might also be provided via DT
29 * with "brcm,bmips-cbr-reg" in the "cpus" node.
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| D | prom.c | 25 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
|
| /linux-6.12.1/tools/perf/util/intel-pt-decoder/ |
| D | intel-pt-decoder.c | 188 unsigned int cbr; member
775 unsigned int cbr; member
813 unsigned int cbr; in intel_pt_calc_cyc_cb() local
933 cbr = pkt_info->packet.payload; in intel_pt_calc_cyc_cb()
934 if (data->cbr && data->cbr != cbr) in intel_pt_calc_cyc_cb()
936 data->cbr = cbr; in intel_pt_calc_cyc_cb()
937 data->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr; in intel_pt_calc_cyc_cb()
953 if (!data->cbr && decoder->cbr) { in intel_pt_calc_cyc_cb()
954 data->cbr = decoder->cbr; in intel_pt_calc_cyc_cb()
963 if (data->cbr && cyc_to_tsc > data->cbr_cyc_to_tsc && in intel_pt_calc_cyc_cb()
[all …]
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| /linux-6.12.1/drivers/atm/ |
| D | iphase.h | 31 Add the CBR support.
238 #define CBR 0x0000 macro
270 u_short out_of_rate_link; /* reserved for UBR and CBR */
574 #define CBR_SCHED_TABLE 0x1800 /* CBR Table */
651 ffreg_t cbr_base; /* CBR Pointer Base */
662 ffreg_t cbr_tab_beg; /* CBR Table Begin */
663 ffreg_t cbr_tab_end; /* CBR Table End */
664 ffreg_t cbr_pointer; /* CBR Pointer */
701 ffreg_t cbr_vc; /* CBR VC */
809 u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
[all …]
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| D | iphase.c | 31 Add the CBR support.
476 IF_ERR(printk("PCR for CBR not defined\n");) in ia_cbr_setup()
481 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n", in ia_cbr_setup()
484 IF_CBR(printk("CBR: Bandwidth smaller than granularity of CBR table\n");) in ia_cbr_setup()
490 IF_CBR(printk("CBR: Not enough bandwidth to support this PCR.\n");) in ia_cbr_setup()
533 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\n", in ia_cbr_setup()
558 IF_CBR(printk("Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\n", in ia_cbr_setup()
562 // Move this VCI number into this location of the CBR Sched table. in ia_cbr_setup()
572 IF_CBR(printk("CBR is enabled\n");) in ia_cbr_setup()
586 IF_CBR (printk("CBR support disabled\n");) in ia_cbrVc_close()
[all …]
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| D | lanai.c | 19 * in CBR at once
446 #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */
634 vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */
760 * boundless if there's a CBR VCC holding things up.
780 * TODO: maybe disable CBR if we're about to timeout? in lanai_shutdown_tx_vci()
1034 #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */
2042 /* -------------------- MANAGE CBR: */
2045 * CBR ICG is stored as a fixed-point number with 4 fractional bits.
2195 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ in lanai_dev_open()
2523 "tx_buf_size=%zu, tx_qos=%cBR, tx_backlogged=%c", in lanai_proc_read()
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| /linux-6.12.1/drivers/misc/sgi-gru/ |
| D | grutables.h | 365 unsigned char ts_cbr_au_count;/* Number of CBR resources
371 signed char ts_cbr_idx[GRU_CBR_AU];/* CBR numbers of each
491 #define CBR_BYTES(cbr) ((cbr) * GRU_HANDLE_BYTES * GRU_CBR_AU_SIZE * 2) argument
523 /* Scan each CBR whose bit is set in a TFM (or copy of) */
527 /* Scan each CBR in a CBR bitmap. Note: multiple CBRs in an allocation unit */
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| D | grukservices.h | 16 * Processes SENDING messages will use a kernel CBR/DSR to send
188 * cb - pointer to first CBR
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| D | grumain.c | 619 "err %d: cch %p, gts %p, cbr 0x%lx, dsr 0x%lx\n", in gru_load_context()
780 int ctxnum, ctxnum0, flag = 0, cbr, dsr; in gru_steal_context() local
786 cbr = gts->ts_cbr_au_count; in gru_steal_context()
802 if (check_gru_resources(gru, cbr, dsr, GRU_NUM_CCH)) in gru_steal_context()
842 gru->gs_gid, ctxnum, ngts, cbr, dsr, hweight64(gru->gs_cbr_map), in gru_steal_context()
902 "gseg %p, gts %p, gid %d, ctx %d, cbr %d, dsr %d\n", in gru_assign_gru_context()
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| D | gruprocfs.c | 193 seq_puts(file, "# gid nid ctx cbr dsr ctx cbr dsr\n"); in gru_seq_show()
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| D | grukservices.c | 269 * Free the current cpus reserved DSR/CBR resources.
354 * cb - pointer to first CBR
964 printk(KERN_DEBUG "GRU:%d quicktest0: CBR failure 1\n", smp_processor_id()); in quicktest0()
974 printk(KERN_DEBUG "GRU:%d quicktest0: CBR failure 2\n", smp_processor_id()); in quicktest0()
1091 gen->istatus = CBS_CALL_OS; /* don't handle this CBR again */ in quicktest2()
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| D | grufault.c | 348 * cb Address of user CBR. Null if not running in user context
456 /* Atomic failure switch CBR to UPM */ in gru_try_dropin()
493 /* All errors (atomic & non-atomic) switch CBR to EXCEPTION state */ in gru_try_dropin()
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| /linux-6.12.1/arch/mips/bcm47xx/ |
| D | setup.c | 50 * CBR addr doesn't change and we can cache it.
51 * For broken SoC/Bootloader CBR addr might also be provided via DT
52 * with "brcm,bmips-cbr-reg" in the "cpus" node.
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| /linux-6.12.1/Documentation/networking/device_drivers/atm/ |
| D | iphase.rst | 26 - UBR, ABR and CBR service categories are supported.
163 c. For CBR test:
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| /linux-6.12.1/drivers/net/wireless/ath/ath5k/ |
| D | reg.h | 187 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
325 #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
326 #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
425 #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
426 #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
588 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
590 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
626 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
627 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
[all …]
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| /linux-6.12.1/arch/mips/include/asm/ |
| D | bmips.h | 19 /* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
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| /linux-6.12.1/arch/sh/kernel/cpu/sh4a/ |
| D | ubc.c | 27 /* CBR */
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| /linux-6.12.1/drivers/staging/vc04_services/bcm2835-camera/ |
| D | bcm2835-camera.h | 77 /* H264 bitrate mode. CBR/VBR */
|