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/linux-6.12.1/arch/arm/include/asm/
Dglue-df.h22 * v5t_early - ARMv5 with Thumb early abort handler
23 * v5tj_early - ARMv5 with Thumb and Java early abort handler
24 * xscale - ARMv5 with Thumb with Xscale extensions
Dcache.h21 * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
Dprocessor.h105 * Prefetching support - only ARMv5.
Dbitops.h228 * On ARMv5 and above, the gcc built-ins may rely on the clz instruction
/linux-6.12.1/Documentation/arch/arm/
Dmarvell.rst32 Feroceon 88fr331 (88f51xx) or 88fr531-vd (88f52xx) ARMv5 compatible
80 Feroceon 88fr131 ARMv5 compatible
112 Feroceon 88fr571-vd ARMv5 compatible
287 ARMv5 compatible
339 - Core: ARMv5 XScale1 core
347 - Core: ARMv5 XScale2 core
358 - Core: ARMv5 XScale3 core
361 - Core: ARMv5 XScale3 core
393 - Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk)
398 - Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk)
[all …]
/linux-6.12.1/arch/arm/mach-sunxi/
DKconfig74 bool "Allwinner ARMv5 F-series (suniv) SoCs support"
78 Support for Allwinner suniv ARMv5 SoCs.
/linux-6.12.1/arch/arm/mach-mmp/
DKconfig17 bool "Support MMP (ARMv5) platforms from device tree"
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
/linux-6.12.1/arch/arm/probes/
Ddecode.h56 /* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
84 /* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */
/linux-6.12.1/arch/arm/
DKconfig.platforms27 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
/linux-6.12.1/arch/arm/mm/
Dfsr-2level.c4 * The following are the standard ARMv3 and ARMv4 aborts. ARMv5
Dcache-tauros2.c225 mode = "ARMv5"; in tauros2_internal_init()
Dproc-macros.S193 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
Ddump.c168 #else /* ARMv4/ARMv5 */
DKconfig764 The only ARMv5 platform with big-endian support is
Dmmu.c478 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those in build_mem_type_table()
489 * ARMv5 and lower, bit 4 must be set for page tables (was: cache in build_mem_type_table()
/linux-6.12.1/arch/arm/mach-versatile/
DKconfig177 platform. On an ARMv5 kernel, this will include support for
/linux-6.12.1/arch/arm/kernel/
Dtcm.c270 * Prior to ARMv5 there is no TCM, and trying to read the status in tcm_init()
/linux-6.12.1/drivers/perf/
Darm_xscale_pmu.c3 * ARMv5 [xscale] Performance counter handling code.
/linux-6.12.1/scripts/dtc/libfdt/
Dlibfdt.h131 * to work even with unaligned pointers on platforms (such as ARMv5) that don't