| /linux-6.12.1/drivers/clk/sprd/ |
| D | sc9860-clk.c | 500 static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
602 static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
826 static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
828 static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
830 static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
832 static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
834 static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
836 static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
838 static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
840 static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/timestamp/ |
| D | nvidia,tegra194-hte.yaml | 19 GPIO lines from the AON (always on) GPIO controller.
24 - nvidia,tegra194-gte-aon
26 - nvidia,tegra234-gte-aon
49 property and the value depends on the HTE instance in the chip. The AON
57 The phandle to AON gpio controller instance. This is required to handle
80 - nvidia,tegra194-gte-aon
81 - nvidia,tegra234-gte-aon
114 - nvidia,tegra234-gte-aon
124 compatible = "nvidia,tegra194-gte-aon";
|
| /linux-6.12.1/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 21 = Always-On control block (AON CTRL)
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
31 "brcm,brcmstb-aon-ctrl"
32 - reg : the register start and length for the AON CTRL block
37 compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
|
| /linux-6.12.1/drivers/clk/ti/ |
| D | clk-33xx.c | 151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
245 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
250 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
251 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
252 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | sprd,sc9860-clk.yaml | 19 - sprd,sc9860-aon-gate
20 - sprd,sc9860-aon-prediv
62 - sprd,sc9860-aon-gate
94 - sprd,sc9860-aon-prediv
106 - sprd,sc9860-aon-prediv
123 - sprd,sc9860-aon-gate
|
| D | brcm,kona-ccu.yaml | 25 - brcm,bcm11351-aon-ccu
30 - brcm,bcm21664-aon-ccu
56 const: brcm,bcm11351-aon-ccu
123 const: brcm,bcm21664-aon-ccu
|
| D | sprd,sc9863a-clk.yaml | 22 - sprd,sc9863a-aon-clk
61 - sprd,sc9863a-aon-clk
|
| /linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
83 - nvidia,tegra186-gpio-aon
85 - nvidia,tegra194-gpio-aon
87 - nvidia,tegra234-gpio-aon
166 - nvidia,tegra186-gpio-aon
167 - nvidia,tegra194-gpio-aon
168 - nvidia,tegra234-gpio-aon
205 compatible = "nvidia,tegra186-gpio-aon";
|
| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra234-pinmux-aon.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
15 const: nvidia,tegra234-pinmux-aon
68 compatible = "nvidia,tegra234-pinmux-aon";
|
| D | starfive,jh7110-aon-pinctrl.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
7 title: StarFive JH7110 AON Pin Controller
22 const: starfive,jh7110-aon-pinctrl
103 compatible = "starfive,jh7110-aon-pinctrl";
|
| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 187 val = readl(pll->control_base + ctrl->aon.offset); in __pll_disable()
188 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
189 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_disable()
194 val = readl(pll->pwr_base + ctrl->aon.offset); in __pll_disable()
195 val |= 1 << ctrl->aon.iso_shift; in __pll_disable()
196 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
199 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
200 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
210 val = readl(pll->control_base + ctrl->aon.offset); in __pll_enable()
211 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
[all …]
|
| D | clk-bcm281xx.c | 31 /* AON CCU */
61 BCM281XX_CCU_COMMON(aon, AON),
64 KONA_CLK(aon, hub_timer, peri),
66 KONA_CLK(aon, pmu_bsc, peri),
68 KONA_CLK(aon, pmu_bsc_var, peri),
|
| D | clk-sr.c | 37 .aon = AON_VAL(0x0, 5, 1, 0),
97 .aon = AON_VAL(0x0, 1, 13, 12),
156 .aon = AON_VAL(0x0, 1, 19, 18),
191 .aon = AON_VAL(0x0, 1, 25, 24),
245 .aon = AON_VAL(0x0, 1, 1, 0),
283 .aon = AON_VAL(0x0, 2, 19, 18),
328 .aon = AON_VAL(0x0, 2, 22, 21),
367 .aon = AON_VAL(0x0, 2, 25, 24),
|
| D | clk-bcm21664.c | 30 /* AON CCU */
43 BCM21664_CCU_COMMON(aon, AON),
50 KONA_CLK(aon, hub_timer, peri),
|
| /linux-6.12.1/include/linux/firmware/imx/ |
| D | sm.h | 13 #define SCMI_IMX_CTRL_PDM_CLK_SEL 0 /* AON PDM clock sel */
14 #define SCMI_IMX_CTRL_MQS1_SETTINGS 1 /* AON MQS settings */
15 #define SCMI_IMX_CTRL_SAI1_MCLK 2 /* AON SAI1 MCLK */
|
| /linux-6.12.1/Documentation/devicetree/bindings/soc/starfive/ |
| D | starfive,jh7110-syscon.yaml | 25 - starfive,jh7110-aon-syscon
59 const: starfive,jh7110-aon-syscon
88 compatible = "starfive,jh7110-aon-syscon", "syscon";
|
| /linux-6.12.1/drivers/pinctrl/starfive/ |
| D | pinctrl-starfive-jh7110-aon.c | 3 * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
159 .compatible = "starfive,jh7110-aon-pinctrl",
169 .name = "starfive-jh7110-aon-pinctrl",
176 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller");
|
| /linux-6.12.1/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 128 = Always-On control block (AON CTRL)
134 - compatible : should contain "brcm,brcmstb-aon-ctrl"
135 - reg : the register start and length for the AON CTRL block
139 aon-ctrl@410000 {
140 compatible = "brcm,brcmstb-aon-ctrl";
|
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | bcm21664.h | 17 #define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu"
26 /* aon CCU clock ids */
|
| D | bcm281xx.h | 22 #define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
32 /* aon CCU clock ids */
|
| /linux-6.12.1/Documentation/devicetree/bindings/arm/omap/ |
| D | prcm.txt | 22 "ti,omap5-cm-core-aon"
26 "ti,dra7-cm-core-aon"
|
| /linux-6.12.1/Documentation/devicetree/bindings/mtd/ |
| D | qcom,nandc.yaml | 32 - const: aon
147 clock-names = "core", "aon";
190 clock-names = "core", "aon";
|
| /linux-6.12.1/Documentation/devicetree/bindings/ufs/ |
| D | sprd,ums9620-ufs.yaml | 47 sprd,aon-apb-syscon:
78 sprd,aon-apb-syscon = <&aon_apb_regs>;
|
| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm7445.dtsi | 145 aon-ctrl@410000 {
146 compatible = "brcm,brcmstb-aon-ctrl";
148 reg-names = "aon-ctrl", "aon-sram";
|
| /linux-6.12.1/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra234-cbb.yaml | 17 which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
45 - nvidia,tegra234-aon-fabric
|