Home
last modified time | relevance | path

Searched +full:ain1 +full:- +full:ain2 (Results 1 – 25 of 36) sorted by relevance

12

/linux-6.12.1/include/media/i2c/
Dadv7183.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * adv7183.h - definition for adv7183 inputs and outputs
12 #define ADV7183_COMPOSITE0 0 /* CVBS in on AIN1 */
13 #define ADV7183_COMPOSITE1 1 /* CVBS in on AIN2 */
24 #define ADV7183_SVIDEO0 11 /* Y on AIN1, C on AIN4 */
25 #define ADV7183_SVIDEO1 12 /* Y on AIN2, C on AIN5 */
28 #define ADV7183_COMPONENT0 14 /* Y on AIN1, Pr on AIN4, Pb on AIN5 */
29 #define ADV7183_COMPONENT1 15 /* Y on AIN2, Pr on AIN3, Pb on AIN6 */
/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Dti,ads1119.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com>
13 The TI ADS1119 is a precision 16-bit ADC over I2C that offers single-ended and
28 reset-gpios:
31 avdd-supply: true
32 dvdd-supply: true
34 vref-supply:
38 "#address-cells":
[all …]
Dti,ads1015.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
19 - ti,ads1015
20 - ti,ads1115
21 - ti,tla2021
22 - ti,tla2024
30 "#address-cells":
33 "#size-cells":
[all …]
/linux-6.12.1/arch/arm/boot/dts/socionext/
Duniphier-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2017 Socionext Inc.
14 pinctrl_ain1: ain1 {
15 groups = "ain1";
16 function = "ain1";
19 pinctrl_ain2: ain2 {
20 groups = "ain2";
21 function = "ain2";
59 pinctrl_ether_mii: ether-mii {
64 pinctrl_ether_rgmii: ether-rgmii {
[all …]
/linux-6.12.1/Documentation/hwmon/
Dpcf8591.rst17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
35 - mode 1 : three differential inputs
37 Pins AIN0 to AIN2 are positive differential inputs for channels 0 to 2
39 - mode 2 : single ended and differential mixed
[all …]
/linux-6.12.1/sound/soc/codecs/
Dak5558.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <sound/soc-dapm.h>
78 "Sharp Roll-Off", "Slow Roll-Off",
79 "Short Delay Sharp Roll-Off", "Short Delay Slow Roll-Off",
99 SND_SOC_DAPM_INPUT("AIN1"),
100 SND_SOC_DAPM_INPUT("AIN2"),
122 SND_SOC_DAPM_INPUT("AIN1"),
123 SND_SOC_DAPM_INPUT("AIN2"),
132 {"ADC Ch1", NULL, "AIN1"},
135 {"ADC Ch2", NULL, "AIN2"},
[all …]
Dwm8776.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8776.c -- WM8776 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
83 static const DECLARE_TLV_DB_SCALE(hp_tlv, -12100, 100, 1);
84 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
85 static const DECLARE_TLV_DB_SCALE(adc_tlv, -10350, 50, 1);
104 SOC_DAPM_SINGLE("AIN1 Switch", WM8776_ADCMUX, 0, 1, 0),
105 SOC_DAPM_SINGLE("AIN2 Switch", WM8776_ADCMUX, 1, 1, 0),
120 SND_SOC_DAPM_INPUT("AIN1"),
121 SND_SOC_DAPM_INPUT("AIN2"),
[all …]
Dwm8770.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8770.c -- WM8770 ALSA SoC Audio driver
105 regcache_mark_dirty(wm8770->regmap); \
114 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
115 static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
116 static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
192 "AIN1", "AIN2", "AIN3", "AIN4",
230 SND_SOC_DAPM_INPUT("AIN1"),
231 SND_SOC_DAPM_INPUT("AIN2"),
269 { "Capture Mux", "AIN1", "AIN1" },
[all …]
Dmt6351.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6351.c -- mt6351 ALSA SoC audio codec driver
8 #include <linux/dma-mapping.h>
202 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, in set_hp_gain_zero()
204 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, in set_hp_gain_zero()
225 dev_warn(cmpnt->dev, "%s(), error rate %d, return 3", in get_cap_reg_val()
256 dev_warn(cmpnt->dev, "%s(), error rate %d, return 8", in get_play_reg_val()
266 struct snd_soc_component *cmpnt = dai->component; in mt6351_codec_dai_hw_params()
270 dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n", in mt6351_codec_dai_hw_params()
271 __func__, substream->stream, rate); in mt6351_codec_dai_hw_params()
[all …]
Dcs42l51.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Based on cs4270.c - Copyright (c) Freescale Semiconductor
12 * - Only I2C is support. Not SPI
13 * - master mode *NOT* supported
47 unsigned int audio_mode; /* The mode (I2S or left-justified) */
66 ucontrol->value.enumerated.item[0] = 0; in cs42l51_get_chan_mix()
71 ucontrol->value.enumerated.item[0] = 1; in cs42l51_get_chan_mix()
74 ucontrol->value.enumerated.item[0] = 2; in cs42l51_get_chan_mix()
91 switch (ucontrol->value.enumerated.item[0]) { in cs42l51_set_chan_mix()
109 static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
[all …]
Dmt6357.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
19 regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, MT6357_GPIO_MODE2_CLEAR_ALL); in set_playback_gpio()
22 regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET, in set_playback_gpio()
32 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0, in set_playback_gpio()
46 regmap_write(priv->regmap, MT6357_GPIO_MODE3_CLR, MT6357_GPIO_MODE3_CLEAR_ALL); in set_capture_gpio()
49 regmap_write(priv->regmap, MT6357_GPIO_MODE3_SET, in set_capture_gpio()
61 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0, in set_capture_gpio()
79 stage = up ? i : MT6357_HPLOUT_STG_CTRL_VAUDP15_MAX - i; in hp_main_output_ramp()
80 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1, in hp_main_output_ramp()
[all …]
Dtlv320aic31xx.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
12 * and mono/stereo Class-D speaker driver.
36 #include <dt-bindings/sound/tlv320aic31xx.h>
180 u8 ocmv; /* output common-mode voltage */
311 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
313 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
317 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
318 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
[all …]
Dmt6358.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
107 priv->mtkaif_protocol = mtkaif_protocol; in mt6358_set_mtkaif_protocol()
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_set()
117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, in playback_gpio_set()
119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_set()
130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_reset()
132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_reset()
134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, in playback_gpio_reset()
141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, in capture_gpio_set()
[all …]
Dmt6359.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6359.c -- mt6359 ALSA SoC audio codec driver
24 regmap_update_bits(priv->regmap, MT6359_SMT_CON1, 0x3ff0, 0x3ff0); in mt6359_set_gpio_smt()
30 regmap_update_bits(priv->regmap, MT6359_DRV_CON2, 0xffff, 0x8888); in mt6359_set_gpio_driving()
31 regmap_update_bits(priv->regmap, MT6359_DRV_CON3, 0xffff, 0x8888); in mt6359_set_gpio_driving()
32 regmap_update_bits(priv->regmap, MT6359_DRV_CON4, 0x00ff, 0x88); in mt6359_set_gpio_driving()
38 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe); in mt6359_set_playback_gpio()
39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249); in mt6359_set_playback_gpio()
42 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6); in mt6359_set_playback_gpio()
43 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1); in mt6359_set_playback_gpio()
[all …]
Dcs42xx8.h2 * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file
44 #define CS42XX8_VOLAIN1 0x11 /* Volume Control AIN1 */
45 #define CS42XX8_VOLAIN2 0x12 /* Volume Control AIN2 */
58 #define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1)
94 #define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_…
98 #define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_…
104 #define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MF…
125 #define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF…
135 #define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF…
144 /* ADC Control & DAC De-Emphasis (Address 05h) */
[all …]
Dadau1977.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 #include <dt-bindings/sound/adi,adau1977.h>
157 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
173 SND_SOC_DAPM_INPUT("AIN1"),
174 SND_SOC_DAPM_INPUT("AIN2"),
182 { "ADC1", NULL, "AIN1" },
183 { "ADC2", NULL, "AIN2" },
197 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
201 SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
[all …]
Dcs4234.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // cs4234.c -- ALSA SoC CS4234 driver
44 /* -89.92dB to +6.02dB with step of 0.38dB */
45 static const DECLARE_TLV_DB_SCALE(dac_tlv, -8992, 38, 0);
96 regmap_read(cs4234->regmap, CS4234_ADC_CTRL2, &val); in cs4234_dac14_grp_delay_put()
98 ret = -EBUSY; in cs4234_dac14_grp_delay_put()
99 dev_err(component->dev, "Can't change group delay while ADC are ON\n"); in cs4234_dac14_grp_delay_put()
103 regmap_read(cs4234->regmap, CS4234_DAC_CTRL4, &val); in cs4234_dac14_grp_delay_put()
105 ret = -EBUSY; in cs4234_dac14_grp_delay_put()
106 dev_err(component->dev, "Can't change group delay while DAC are ON\n"); in cs4234_dac14_grp_delay_put()
[all …]
/linux-6.12.1/include/linux/platform_data/
Dad7793.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * enum ad7793_clock_source - AD7793 clock source selection
25 * enum ad7793_bias_voltage - AD7793 bias voltage selection
27 * @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
28 * @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
29 * @AD7793_BIAS_VOLTAGE_AIN3: Bias voltage connected to AIN3(-).
40 * enum ad7793_refsel - AD7793 reference voltage selection
42 * and REFIN1(-).
44 * and REFIN1(-). Only valid for AD7795/AD7796.
54 * enum ad7793_current_source_direction - AD7793 excitation current direction
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dti,tlv320dac3100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments - tlv320aic31xx Codec module
10 - Shenghao Ding <shenghao-ding@ti.com>
25 * AIN1, devices without ADC
26 * AIN2, devices without ADC
28 The pins can be used in referring sound node's audio-routing property.
33 - ti,tlv320aic310x # - Generic TLV320AIC31xx with mono speaker amp
34 - ti,tlv320aic311x # - Generic TLV320AIC31xx with stereo speaker amp
[all …]
/linux-6.12.1/drivers/iio/adc/
Dad7192.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
11 #include <linux/clk-provider.h>
35 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
36 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
38 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
39 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
40 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
41 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
[all …]
Dad7793.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2012 Analog Devices Inc.
30 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
33 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
34 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
35 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
37 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
[all …]
/linux-6.12.1/drivers/pinctrl/uniphier/
Dpinctrl-uniphier-ld20.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2016-2017 Socionext Inc.
12 #include "pinctrl-uniphier.h"
199 -1, UNIPHIER_PIN_DRV_FIXED4,
200 -1, UNIPHIER_PIN_PULL_NONE),
202 -1, UNIPHIER_PIN_DRV_FIXED4,
203 -1, UNIPHIER_PIN_PULL_NONE),
205 -1, UNIPHIER_PIN_DRV_FIXED4,
206 -1, UNIPHIER_PIN_PULL_NONE),
208 -1, UNIPHIER_PIN_DRV_FIXED4,
[all …]
Dpinctrl-uniphier-pxs2.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2015-2017 Socionext Inc.
12 #include "pinctrl-uniphier.h"
61 -1, UNIPHIER_PIN_DRV_FIXED8,
64 -1, UNIPHIER_PIN_DRV_FIXED8,
67 -1, UNIPHIER_PIN_DRV_FIXED8,
70 -1, UNIPHIER_PIN_DRV_FIXED8,
73 -1, UNIPHIER_PIN_DRV_FIXED8,
76 -1, UNIPHIER_PIN_DRV_FIXED8,
79 -1, UNIPHIER_PIN_DRV_FIXED8,
[all …]
Dpinctrl-uniphier-pxs3.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-uniphier.h"
328 -1, UNIPHIER_PIN_DRV_FIXED4,
329 -1, UNIPHIER_PIN_PULL_NONE),
331 -1, UNIPHIER_PIN_DRV_FIXED4,
332 -1, UNIPHIER_PIN_PULL_NONE),
334 -1, UNIPHIER_PIN_DRV_FIXED4,
335 -1, UNIPHIER_PIN_PULL_NONE),
337 -1, UNIPHIER_PIN_DRV_FIXED4,
338 -1, UNIPHIER_PIN_PULL_NONE),
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mp-dhcom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
29 regulator-always-on;
30 regulator-boot-on;
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
[all …]

12