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/linux-6.12.1/arch/x86/boot/
Dcpucheck.c57 #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a)) macro
61 return cpu_vendor[0] == A32('A', 'u', 't', 'h') && in is_amd()
62 cpu_vendor[1] == A32('e', 'n', 't', 'i') && in is_amd()
63 cpu_vendor[2] == A32('c', 'A', 'M', 'D'); in is_amd()
68 return cpu_vendor[0] == A32('C', 'e', 'n', 't') && in is_centaur()
69 cpu_vendor[1] == A32('a', 'u', 'r', 'H') && in is_centaur()
70 cpu_vendor[2] == A32('a', 'u', 'l', 's'); in is_centaur()
75 return cpu_vendor[0] == A32('G', 'e', 'n', 'u') && in is_transmeta()
76 cpu_vendor[1] == A32('i', 'n', 'e', 'T') && in is_transmeta()
77 cpu_vendor[2] == A32('M', 'x', '8', '6'); in is_transmeta()
[all …]
/linux-6.12.1/tools/testing/selftests/rseq/
Drseq-arm.h11 * RSEQ_SIG uses the udf A32 instruction with an uncommon immediate operand
16 * The instruction pattern in the A32 instruction set is:
35 * Translates to this A32 instruction pattern:
/linux-6.12.1/arch/arm/include/asm/
Darch_gicv3.h41 #define CPUIF_MAP(a32, a64) \ argument
44 write_sysreg(val, a32); \
48 return read_sysreg(a32); \
/linux-6.12.1/drivers/scsi/be2iscsi/
Dbe_mgmt.h145 bus_address.u.a32.address_lo; \
147 bus_address.u.a32.address_hi; \
Dbe_main.c1538 phys_addr.u.a32.address_lo = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, in beiscsi_hdl_get_handle()
1540 phys_addr.u.a32.address_lo -= dpl; in beiscsi_hdl_get_handle()
1541 phys_addr.u.a32.address_hi = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, in beiscsi_hdl_get_handle()
1761 pasync_sge[pi].hi = pasync_handle->pa.u.a32.address_lo; in beiscsi_hdq_post_handles()
1762 pasync_sge[pi].lo = pasync_handle->pa.u.a32.address_hi; in beiscsi_hdq_post_handles()
2101 io_task->bhs_pa.u.a32.address_lo); in hwi_write_sgl_v2()
2103 io_task->bhs_pa.u.a32.address_hi); in hwi_write_sgl_v2()
2143 io_task->bhs_pa.u.a32.address_hi); in hwi_write_sgl_v2()
2145 io_task->bhs_pa.u.a32.address_lo); in hwi_write_sgl_v2()
2196 io_task->bhs_pa.u.a32.address_lo); in hwi_write_sgl()
[all …]
Dbe_mgmt.c1350 mem_descr->mem_array[0].bus_address.u.a32.address_hi); in beiscsi_offload_cxn_v0()
1353 mem_descr->mem_array[0].bus_address.u.a32.address_lo); in beiscsi_offload_cxn_v0()
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,corstone1000.yaml18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
Dpmu.yaml38 - arm,cortex-a32-pmu
Dcpus.yaml130 - arm,cortex-a32
/linux-6.12.1/include/linux/
Detherdevice.h585 u32 *a32 = (u32 *)((u8 *)a + 2); in compare_ether_header()
588 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
589 (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]); in compare_ether_header()
/linux-6.12.1/arch/arm/kernel/
Dopcodes.c5 * A32 condition code lookup feature moved from nwfpe/fpopcode.c
/linux-6.12.1/drivers/net/ethernet/brocade/bna/
Dbfa_ioc.h55 dma_addr->a32.addr_lo = (u32) htonl(pa); in __bfa_dma_be_addr_set()
56 dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa)); in __bfa_dma_be_addr_set()
Dbna_tx_rx.c1293 (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
1294 (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
1295 (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
1296 (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
1667 cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo = in bna_bfi_rx_enet_start()
1669 cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi = in bna_bfi_rx_enet_start()
3104 cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo = in bna_bfi_tx_enet_start()
3106 cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi = in bna_bfi_tx_enet_start()
Dbfi.h68 } __packed a32; member
Dbfi_enet.h52 } __packed a32; member
/linux-6.12.1/drivers/staging/vme_user/
Dvme_tsi148.h676 #define TSI148_LCSR_OTAT_AMODE_A32 (2 << 0) /* A32 Address Space */
677 #define TSI148_LCSR_OTAT_AMODE_A64 (4 << 0) /* A32 Address Space */
869 #define TSI148_LCSR_ITAT_AS_A32 (2 << 4) /* A32 Address Space */
942 #define TSI148_LCSR_LMAT_AS_A32 (2 << 4) /* A32 */
1284 #define TSI148_LCSR_DSAT_AMODE_A32 (2 << 0) /* A32 */
1321 #define TSI148_LCSR_DDAT_AMODE_A32 (2 << 0) /* A32 */
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
/linux-6.12.1/tools/perf/util/
Dsymbol.h249 Elf32_Addr a32[3]; member
Dsymbol-elf.c2694 tmp->addr.a32[SDT_NOTE_IDX_LOC] = in sdt_adjust_loc()
2695 tmp->addr.a32[SDT_NOTE_IDX_LOC] + base_off - in sdt_adjust_loc()
2696 tmp->addr.a32[SDT_NOTE_IDX_BASE]; in sdt_adjust_loc()
2709 if (tmp->bit32 && tmp->addr.a32[SDT_NOTE_IDX_REFCTR]) in sdt_adjust_refctr()
2710 tmp->addr.a32[SDT_NOTE_IDX_REFCTR] -= (base_addr - base_off); in sdt_adjust_refctr()
2737 Elf32_Addr a32[NR_ADDR]; in populate_sdt_note() member
Dprobe-file.c744 (unsigned long long)note->addr.a32[SDT_NOTE_IDX_LOC] : in sdt_note__get_addr()
751 (unsigned long long)note->addr.a32[SDT_NOTE_IDX_REFCTR] : in sdt_note__get_ref_ctr_offset()
Dcs-etm.c1383 /* Assume a 4 byte instruction size (A32/A64) */ in cs_etm__instr_addr()
1526 /* Otherwise, A64 and A32 instruction size are always 32-bit. */ in cs_etm__copy_insn()
2063 * The SVC of A32 is defined in ARM DDI 0487D.a, F5.1.247: in cs_etm__is_svc_instr()
2248 * function return for A32/T32. in cs_etm__set_sample_flags()
/linux-6.12.1/drivers/scsi/bfa/
Dbfa_ioc.h180 dma_addr->a32.addr_lo = cpu_to_be32(pa); in __bfa_dma_be_addr_set()
181 dma_addr->a32.addr_hi = cpu_to_be32(pa >> 32); in __bfa_dma_be_addr_set()
Dbfa_fcpim.c2464 sgpge->sga.a32.addr_lo = 0; in bfa_ioim_send_ioreq()
2465 sgpge->sga.a32.addr_hi = 0; in bfa_ioim_send_ioreq()
2483 sge->sga.a32.addr_lo = 0; in bfa_ioim_send_ioreq()
2484 sge->sga.a32.addr_hi = 0; in bfa_ioim_send_ioreq()
/linux-6.12.1/drivers/media/usb/gspca/
Dspca501.c129 {0x0, 0x02, 0x0F}, /* A32 */
139 {0x1, 0xf8, 0x0F}, /* A32 f8 */
517 {0x1, 0x0000, 0x000f}, /* CCDSP YUV A32 */
1644 {0x01, 0x00e4, 0x000f}, /* A32 */
/linux-6.12.1/arch/arm64/kernel/
Dprocess.c171 pstate & PSR_AA32_T_BIT ? "T32" : "A32", in print_pstate()

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