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Searched +full:400 +full:khz (Results 1 – 25 of 203) sorted by relevance

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/linux-6.12.1/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
39 { NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
[all …]
/linux-6.12.1/Documentation/i2c/busses/
Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/linux-6.12.1/drivers/i3c/master/mipi-i3c-hci/
Dxfer_mode_rate.h53 #define XFERRATE_I3C_SDR_FM_FMP 0x05 /* 400 KHz / 1 MHz */
57 #define XFERRATE_I2C_FM 0x00 /* 400 KHz */
/linux-6.12.1/Documentation/dev-tools/
Dgpio-sloppy-logic-analyzer.rst67 snippet which analyzes an I2C bus at 400kHz on a Renesas Salvator-XS board, the
70 parameter. The bus speed is 400kHz. So, the sampling theorem says we need to
71 sample at least at 800kHz. However, falling edges of both signals in an I2C
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
Dnuvoton,nau8325.yaml48 FS range is from 8kHz to 96kHz. And also needs to detect the ratio
49 MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
/linux-6.12.1/Documentation/hwmon/
Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
/linux-6.12.1/drivers/clk/spear/
Dspear1340_clock.c167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
179 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
202 * 250, 332, 400 or 500 MHz considering different possibilites of input
208 * 400 200 100 0x04000
209 * 400 250 125 0x03333
210 * 400 332 166 0x0268D
211 * 400 400 200 0x02000
216 * 500 400 200 0x02800
222 * 600 400 200 0x03000
[all …]
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun5i-reference-design-tablet.dtsi88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/linux-6.12.1/drivers/i2c/busses/
Di2c-stm32.h19 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
20 STM32_I2C_SPEED_FAST, /* 400 kHz */
Di2c-stm32f4.c161 * To reach 100 kHz, the parent clk frequency should be between in stm32f4_i2c_set_periph_clk_freq()
173 * To be as close as possible to 400 kHz, the parent clk in stm32f4_i2c_set_periph_clk_freq()
234 * So to reach 100 kHz, we have: in stm32f4_i2c_set_speed_mode()
235 * CCR = I2C parent rate / (100 kHz * 2) in stm32f4_i2c_set_speed_mode()
240 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached in stm32f4_i2c_set_speed_mode()
250 * frequencies we are not able to reach 400 kHz. in stm32f4_i2c_set_speed_mode()
254 * So, CCR = I2C parent rate / (400 kHz * 3) in stm32f4_i2c_set_speed_mode()
260 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached in stm32f4_i2c_set_speed_mode()
Di2c-designware-common.c202 * Only standard mode at 100kHz, fast mode at 400kHz, in i2c_dw_validate_speed()
211 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", in i2c_dw_validate_speed()
545 * transfer supported by the driver (for 400KHz this is in __i2c_dw_disable()
574 * transfer supported by the driver (for 400KHz this is in __i2c_dw_disable()
Di2c-ismt.c147 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
148 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
149 #define ISMT_SPGT_SPD_400K (0x2U << 30) /* 400 kHz */
198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
756 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); in ismt_hw_init()
762 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); in ismt_hw_init()
767 case 400: in ismt_hw_init()
768 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); in ismt_hw_init()
774 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); in ismt_hw_init()
780 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); in ismt_hw_init()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/regulator/
Drichtek,rt6245-regulator.yaml63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/linux-6.12.1/Documentation/devicetree/bindings/iio/pressure/
Dhoneywell,hsc030pa.yaml31 exceed 800kHz and the MOSI signal is not required.
65 400MD, 600MD, 001BD, 1.6BD, 2.5BD, 004BD, 2.5MG, 004MG, 006MG,
66 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
68 250KA, 400KA, 600KA, 001GA, 160LD, 250LD, 400LD, 600LD, 001KD,
70 100KD, 160KD, 250KD, 400KD, 250LG, 400LG, 600LG, 001KG, 1.6KG,
72 160KG, 250KG, 400KG, 600KG, 001GG, 015PA, 030PA, 060PA, 100PA,
/linux-6.12.1/Documentation/devicetree/bindings/tpm/
Dtcg,tpm-tis-i2c.yaml42 - infineon,slb9635tt # TPM 1.2 (maximum 100 kHz)
43 - infineon,slb9645tt # TPM 1.2 (maximum 400 kHz)
/linux-6.12.1/sound/firewire/fireface/
Dff-protocol-latter.c62 // 0x00: 32.0 kHz
63 // 0x01: 44.1 kHz
64 // 0x02: 48.0 kHz
65 // 0x04: 64.0 kHz
66 // 0x05: 88.2 kHz
67 // 0x06: 96.0 kHz
68 // 0x08: 128.0 kHz
69 // 0x09: 176.4 kHz
70 // 0x0a: 192.0 kHz
269 // IEEE 1394a (400 Mbps), Analog 1-12 and AES are available in latter_begin_session()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml45 frequency is fixed at 100 KHz.
109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
/linux-6.12.1/include/linux/
Dwm97xx.h53 #define WM97XX_CM_RATE_8K 0x00f0 /* 8kHz continuous rate */
54 #define WM97XX_CM_RATE_12K 0x01f0 /* 12kHz continuous rate */
55 #define WM97XX_CM_RATE_24K 0x02f0 /* 24kHz continuous rate */
56 #define WM97XX_CM_RATE_48K 0x03f0 /* 48kHz continuous rate */
74 #define WM9712_PIL 0x0100 /* current used for pressure measurement. set 400uA else 200uA */
91 #define WM9705_PIL 0x0080 /* current used for pressure measurement. set 400uA else 200uA */
Dclocksource.h54 * @freq_khz: Clocksource frequency in khz.
67 * 400-499: Perfect
171 * clocksource_khz2mult - calculates mult from khz and shift
172 * @khz: Clocksource frequency in KHz
175 * Helper functions that converts a khz counter frequency to a timsource
178 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
180 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
234 * clocksource_register_hz/khz
255 static inline int clocksource_register_khz(struct clocksource *cs, u32 khz) in clocksource_register_khz() argument
257 return __clocksource_register_scale(cs, 1000, khz); in clocksource_register_khz()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dmax9877.c32 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
51 "1176KHz",
52 "1100KHz",
53 "700KHz",
Dmax9860.c133 static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
137 "AGC Disabled", "50ms", "100ms", "400ms"
167 "Elliptical HP 217Hz notch (16kHz)",
168 "Butterworth HP 500Hz (16kHz)",
169 "Elliptical HP 217Hz notch (8kHz)",
170 "Butterworth HP 500Hz (8kHz)",
171 "Butterworth HP 200Hz (48kHz)"
393 * 65536 * 96 * 48kHz / 10MHz -> 30199 in max9860_hw_params()
395 * 65536 * 96 * 8kHz / 20MHz -> 2517 in max9860_hw_params()
/linux-6.12.1/drivers/media/radio/
Dlm7000.h29 freq /= 400; /* Convert to 25 kHz units */ in lm7000_set_freq()
/linux-6.12.1/drivers/i2c/
Di2c-core-acpi.c347 * These Silead touchscreen controllers only work at 400KHz, for
348 * some reason they do not work at 100KHz. On some devices the ACPI
350 * of 100KHz, testing has shown that these other devices work fine
351 * at 400KHz (as can be expected of any recent i2c hw) so we force
352 * the speed of the bus to 400 KHz if a Silead device is present.

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