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/linux-6.12.1/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
81 # Scan Frequency 50.900 kHz 100.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
102 # Scan Frequency 61.800 kHz 120.00 Hz
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/linux-6.12.1/sound/pci/ca0106/
Dca0106.h68 /* DATA[31:0] */
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
170 /* ADDR[31:0], Default: 0x0 */
177 /* DMA[31:0], Default: 0x0 */
179 /* SIZE[31:16], Default: 0x0 */
188 /* DMA[31:0], Default: 0x0 */
190 /* SIZE[31:16], Default: 0x0 */
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
205 * Playback mixer out enable [31:28] (one bit per channel)
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
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/linux-6.12.1/sound/pci/emu10k1/
Dp16v.h83 * [31:27] Not used.
93 * [18:16] Channel 0 Detected sample rate. 0 - 44.1khz
94 * 1 - 48 khz
95 * 2 - 96 khz
96 * 3 - 192 khz
104 * [31] Channel 3. 1 - Valid, 0 - Not Valid.
147 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
148 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
174 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
176 * [31:24] The corresponding E10K2 channel to SRC48 enabled.
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.h27 #define KHZ (1000) macro
28 #define MHZ (KHZ * 1000)
68 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31
81 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31
101 /* All frequencies in Khz */
146 clk->parent_rate / KHZ); in gk20a_pllg_n_lo()
/linux-6.12.1/sound/soc/codecs/
Dmax9877.c35 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
51 "1176KHz",
52 "1100KHz",
53 "700KHz",
69 MAX9877_SPK_VOLUME, 0, 31, 0, max9877_output_tlv),
71 MAX9877_HPL_VOLUME, MAX9877_HPR_VOLUME, 0, 31, 0,
/linux-6.12.1/drivers/gpu/drm/tests/
Ddrm_kunit_edid.h9 * 00 ff ff ff ff ff ff 00 31 d8 2a 00 00 00 00 00
41 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
46 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
67 * 00 ff ff ff ff ff ff 00 31 d8 2a 00 00 00 00 00
106 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
109 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
114 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
128 * VIC 16: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz
169 * 00 ff ff ff ff ff ff 00 31 d8 2a 00 00 00 00 00
208 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
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/linux-6.12.1/drivers/clk/pxa/
Dclk-pxa2xx.h14 #define CCCR_CPDIS_BIT (31)
24 #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
55 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
56 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dstericsson,u8500-clks.yaml17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
54 wants, possible values are 0 thru 31.
68 values are 0 thru 31.
82 it wants to control, possible values are 0 thru 31.
92 description: A subnode with zero clock cells for the 32kHz RTC clock.
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6q.dtsi25 /* kHz uV */
33 /* ARM kHz SOC-PU uV */
62 /* kHz uV */
70 /* ARM kHz SOC-PU uV */
97 /* kHz uV */
105 /* ARM kHz SOC-PU uV */
132 /* kHz uV */
140 /* ARM kHz SOC-PU uV */
321 <&iomuxc 31 44 1>;
340 <&iomuxc 31 86 1>;
Dimx6dl.dtsi24 /* kHz uV */
30 /* ARM kHz SOC-PU uV */
57 /* kHz uV */
63 /* ARM kHz SOC-PU uV */
136 <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
157 <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
173 <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
Dimx6q-cm-fx6.dts63 gpios = <&gpio2 31 0>;
185 /* kHz uV */
192 /* ARM kHz SOC-PU uV */
207 /* kHz uV */
214 /* ARM kHz SOC-PU uV */
229 /* kHz uV */
236 /* ARM kHz SOC-PU uV */
251 /* kHz uV */
258 /* ARM kHz SOC-PU uV */
/linux-6.12.1/drivers/media/radio/si470x/
Dradio-si470x-common.c57 * 2008-01-31 Tobias Lorenz <tobias.lorenz@gmx.net>
86 * 2009-01-31 Bob Ross <pigiron@gmx.com>
89 * 2009-01-31 Rick Bronson <rick@efn.org>
108 /* Spacing (kHz) */
109 /* 0: 200 kHz (USA, Australia) */
110 /* 1: 100 kHz (Europe, Japan) */
111 /* 2: 50 kHz */
114 MODULE_PARM_DESC(space, "Spacing: 0=200kHz 1=100kHz *2=50kHz*");
241 /* Spacing (kHz) */ in si470x_get_step()
243 /* 0: 200 kHz (USA, Australia) */ in si470x_get_step()
[all …]
/linux-6.12.1/arch/arm/mach-omap1/
Dtimer32k.c59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
167 * 32KHz clocksource ... always available, on pretty most chips except
222 * The 'SCHEME' bits(30-31) of the revision register is used in omap_init_clocksource_32k()
Di2c.c76 #define OMAP_I2C_CMDLINE_SETUP (BIT(31))
85 * Format: i2c_bus=bus_id,clkrate (in kHz)
127 * @clkrate: clock rate of the bus in kHz
/linux-6.12.1/drivers/i3c/master/mipi-i3c-hci/
Dxfer_mode_rate.h53 #define XFERRATE_I3C_SDR_FM_FMP 0x05 /* 400 KHz / 1 MHz */
57 #define XFERRATE_I2C_FM 0x00 /* 400 KHz */
75 #define XFERRATE_MODE_ID GENMASK(31, 28)
/linux-6.12.1/Documentation/arch/m68k/
Dkernel-options.rst532 the horizontal frequency, in kHz.
534 The defaults are 58;62;31;32 (VGA compatible).
727 - ntsc : 640x200, 15 kHz, 60 Hz
728 - ntsc-lace : 640x400, 15 kHz, 60 Hz interlaced
731 - pal : 640x256, 15 kHz, 50 Hz
732 - pal-lace : 640x512, 15 kHz, 50 Hz interlaced
735 - multiscan : 640x480, 29 kHz, 57 Hz
736 - multiscan-lace : 640x960, 29 kHz, 57 Hz interlaced
737 - euro36 : 640x200, 15 kHz, 72 Hz
738 - euro36-lace : 640x400, 15 kHz, 72 Hz interlaced
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dfsl,xcvr.yaml54 - description: PLL clock source for 8kHz series
55 - description: PLL clock source for 11kHz series
157 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
/linux-6.12.1/drivers/cpufreq/
Dtegra194-cpufreq.c21 #define KHZ 1000 macro
23 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
95 opp = dev_pm_opp_find_freq_exact(dev, freq_khz * KHZ, true); in tegra_cpufreq_set_bw()
147 * [31:0] Core clock counter: Counts on every core clock cycle
224 * [31:0] PLLP counter: Counts at fixed frequency (408 MHz)
240 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
308 * - Return Kcycles/second, freq in KHz
315 * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
318 * Returns freq in KHz on success, 0 if cpu is offline
356 return (rate_mhz * KHZ); /* in KHz */ in tegra194_calculate_speed()
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Dpxa2xx-cpufreq.c6 * 31-Jul-2002 : Initial version [FB]
51 unsigned int khz; member
195 new_freq_cpu = pxa_freq_settings[idx].khz; in pxa_set_target()
242 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; in pxa_cpufreq_init()
250 pxa255_turbo_freqs[i].khz; in pxa_cpufreq_init()
259 freq = pxa27x_freqs[i].khz; in pxa_cpufreq_init()
/linux-6.12.1/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
71 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
75 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dmc_regs.h53 #define DMC_EVT_CTL_ENABLE REG_BIT(31)
64 /* An event handler scheduled to run at a 1 kHz frequency. */
101 #define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
103 #define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
/linux-6.12.1/drivers/media/dvb-frontends/
Dstb6100.c270 if (bandwidth >= 36000000) /* F[4:0] BW/2 max =31+5=36 mhz for F=31 */ in stb6100_set_bandwidth()
271 tmp = 31; in stb6100_set_bandwidth()
318 "frequency = %u kHz, odiv = %u, psd2 = %u, fxtal = %u kHz, fvco = %u kHz, N(I) = %u, N(F) = %u", in stb6100_get_frequency()
371 printk(KERN_ERR "%s: frequency out of range: %u kHz\n", __func__, frequency); in stb6100_set_frequency()
496 state->reference = refclk / 1000; /* kHz */ in stb6100_init()
544 state->reference = config->refclock / 1000; /* kHz */ in stb6100_attach()
/linux-6.12.1/drivers/devfreq/
Dtegra30-devfreq.c38 #define ACTMON_DEV_CTRL_ENB BIT(31)
53 #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31)
68 #define KHZ 1000 macro
70 #define KHZ_MAX (ULONG_MAX / KHZ)
94 * Threshold of activity (cycles translated to kHz) below which the
125 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
147 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
154 * Frequencies are in kHz.
254 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
412 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_clk_notify_cb()
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/linux-6.12.1/Documentation/translations/zh_CN/power/
Denergy-model.rst171 02 unsigned long *KHz)
176 07 freq = foo_get_freq_ceil(dev, *KHz);
187 18 *KHz = freq;
200 31 /* 查找该策略支持的OPP数量 */
/linux-6.12.1/drivers/gpu/drm/radeon/
Drv770d.h130 #define PDNB (1 << 31)
205 # define MRDCKD1_BYPASS (1 << 31)
353 #define RB_RPTR_WR_ENA (1 << 31)
405 #define GUI_ACTIVE (1<<31)
541 #define BARYC_AT_SAMPLE_ENA (1<<31)
605 #define BILINEAR_PRECISION_6_BIT (0 << 31)
606 #define BILINEAR_PRECISION_8_BIT (1 << 31)
750 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
831 # define AFMT_RAMP_DATA_SIGN (1 << 31)
892 * bit0 = 32 kHz
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