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Searched +full:2 +full:c001000 (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv2.dtsi8 gic: interrupt-controller@2c001000 {
Dvexpress-v2f-1xv7-ca53x2.dts8 * Cortex-A53 (2 cores) Soft Macrocell Model
24 #address-cells = <2>;
25 #size-cells = <2>;
41 #address-cells = <2>;
60 cache-level = <2>;
67 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
71 #address-cells = <2>;
72 #size-cells = <2>;
75 /* Chipselect 2 is physically at 0x18000000 */
84 gic: interrupt-controller@2c001000 {
[all …]
Drtsm_ve-aemv8a.dts23 #address-cells = <2>;
24 #size-cells = <2>;
38 #address-cells = <2>;
57 cpu@2 {
76 cache-level = <2>;
88 #address-cells = <2>;
89 #size-cells = <2>;
92 /* Chipselect 2,00000000 is physically at 0x18000000 */
101 gic: interrupt-controller@2c001000 {
144 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
/linux-6.12.1/arch/arm/boot/dts/xen/
Dxenvm-4.2.dts16 #address-cells = <2>;
17 #size-cells = <2>;
45 cpu_on = <2>;
54 gic: interrupt-controller@2c001000 {
/linux-6.12.1/Documentation/devicetree/bindings/mailbox/
Dst,stm32-ipcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
64 ipcc: mailbox@4c001000 {
/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dst,stm32-etzpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
84 usart2: serial@4c001000 {
/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca5s.dts63 /* Chipselect 2 is physically at 0x18000000 */
72 hdlcd@2a110000 {
80 memory-controller@2a150000 {
87 memory-controller@2a190000 {
96 scu@2c000000 {
101 timer@2c000600 {
107 timer@2c000200 {
115 watchdog@2c000620 {
121 gic: interrupt-controller@2c001000 {
130 L2: cache-controller@2c0f0000 {
[all …]
Dvexpress-v2p-ca15-tc1.dts20 #address-cells = <2>;
21 #size-cells = <2>;
57 #address-cells = <2>;
58 #size-cells = <2>;
61 /* Chipselect 2 is physically at 0x18000000 */
70 hdlcd@2b000000 {
78 memory-controller@2b0a0000 {
85 wdt@2b060000 {
94 gic: interrupt-controller@2c001000 {
202 arm,vexpress-sysreg,func = <2 0>;
[all …]
Dvexpress-v2p-ca15_a7.dts20 #address-cells = <2>;
21 #size-cells = <2>;
58 cpu2: cpu@2 {
113 #address-cells = <2>;
114 #size-cells = <2>;
117 /* Chipselect 2 is physically at 0x18000000 */
126 wdt@2a490000 {
134 hdlcd@2b000000 {
142 memory-controller@2b0a0000 {
149 gic: interrupt-controller@2c001000 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml67 enum: [ 0, 1, 2 ]
69 enum: [ 1, 2 ]
77 The 2nd cell contains the interrupt number for the interrupt type.
84 2 = high-to-low edge triggered (invalid for SPIs)
98 first region is the GIC distributor register base and size. The 2nd region
104 control register base and size. The 2nd additional region is the GIC
106 minItems: 2
125 maxItems: 2
203 interrupt-controller@2c001000 {
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp151.dtsi126 ipcc: mailbox@4c001000 {
178 #interrupt-cells = <2>;
481 timer@2 {
483 reg = <2>;
927 dac2: dac@2 {
930 reg = <2>;
1327 dfsdm2: filter@2 {
1330 reg = <2>;
1564 trigger@2 {
1566 reg = <2>;
[all …]
Dstm32mp131.dtsi71 scmi_usb33: regulator@2 {
169 timer@2 {
171 reg = <2>;
788 #interrupt-cells = <2>;
1074 usart2: serial@4c001000 {
1392 access-controllers = <&etzpc 2>;
1401 trigger@2 {
1403 reg = <2>;
1438 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1439 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
[all …]