Searched +full:2 +full:b1f0000 (Results 1 – 8 of 8) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 17 mhu: mhu0@2b1f0000 {
24 clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
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| /linux-6.12.1/Documentation/devicetree/bindings/mailbox/ |
| D | arm,mhuv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
14 The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
111 mhu: mailbox@2b1f0000 {
114 arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
133 It is always set to 2. The first argument in the consumers 'mboxes'
144 mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
148 const: 2
172 #address-cells = <2>;
173 #size-cells = <2>;
175 mhu_tx: mailbox@2b1f0000 {
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| D | arm,mhu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
60 minItems: 2
76 Set to 2 in doorbell mode and represents index of the channel and doorbell
78 enum: [ 1, 2 ]
92 #address-cells = <2>;
93 #size-cells = <2>;
95 mhuA: mailbox@2b1f0000 {
102 clocks = <&clock 0 2 1>;
115 num-domains = <2>;
124 #address-cells = <2>;
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| /linux-6.12.1/Documentation/devicetree/bindings/rtc/ |
| D | ti,k3-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
54 rtc@2b1f0000 {
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| /linux-6.12.1/arch/arm64/boot/dts/ti/ |
| D | k3-am62a-wakeup.dtsi | 36 wkup_uart0: serial@2b300000 {
46 wkup_i2c0: i2c@2b200000 {
58 wkup_rtc0: rtc@2b1f0000 {
68 wkup_rti0: watchdog@2b000000 {
74 assigned-clock-parents = <&k3_clks 132 2>;
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| D | k3-am62-wakeup.dtsi | 41 target-module@2b300050 {
71 wkup_i2c0: i2c@2b200000 {
83 wkup_rtc0: rtc@2b1f0000 {
93 wkup_rti0: watchdog@2b000000 {
99 assigned-clock-parents = <&k3_clks 132 2>;
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| D | k3-am62p-j722s-common-wakeup.dtsi | 39 wkup_uart0: serial@2b300000 {
49 wkup_i2c0: i2c@2b200000 {
61 wkup_rtc0: rtc@2b1f0000 {
71 wkup_rti0: watchdog@2b000000 {
77 assigned-clock-parents = <&k3_clks 132 2>;
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| /linux-6.12.1/arch/arm64/boot/dts/arm/ |
| D | juno-base.dtsi | 10 memtimer: timer@2a810000 {
18 frame@2a830000 {
25 mailbox: mhu@2b1f0000 {
36 smmu_gpu: iommu@2b400000 {
48 smmu_pcie: iommu@2b500000 {
59 smmu_etr: iommu@2b600000 {
70 gic: interrupt-controller@2c010000 {
446 port@2 {
447 reg = <2>;
585 arm,trig-in-sigs = <2 3>;
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