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/linux-6.12.1/drivers/media/platform/verisilicon/
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
Dhantro_g1_regs.h50 #define G1_REG_DEC_CTRL0_DIVX3_E BIT(25)
86 #define G1_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25)
129 #define G1_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25)
139 #define G1_REG_DEC_CTRL4_AVS_H264_H_EXT BIT(25)
158 #define G1_REG_DEC_CTRL4_PJPEG_WDIV8 BIT(25)
206 #define G1_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25)
219 #define G1_REG_DEC_CTRL7_PINIT_RLIST_F15(x) (((x) & 0x1f) << 25)
260 #define G1_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 25)
278 #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 25)
313 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
[all …]
Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
Dhantro_g1_mpeg2_dec.c25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
[all …]
/linux-6.12.1/arch/arm64/crypto/
Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/linux-6.12.1/arch/alpha/kernel/
Dentry.S79 stq $25, 120($sp)
96 .cfi_rel_offset $25, 120
125 ldq $25, 120($sp)
145 .cfi_restore $25
283 stq $25, 200($sp)
310 .cfi_rel_offset $25, 25*8
342 ldq $25, 200($sp)
369 .cfi_restore $25
691 #define V(n) stt $f##n, FR(n) macro
692 V( 0); V( 1); V( 2); V( 3)
[all …]
/linux-6.12.1/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
87 # 13 chars 25 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
[all …]
/linux-6.12.1/arch/arm64/kvm/hyp/
Daarch32.c32 0xAAAA, /* VS == V set */
36 0xAA55, /* GE == (N==V) */
37 0x55AA, /* LT == (N!=V) */
38 0x0A05, /* GT == (!Z && (N==V)) */
39 0xF5FA, /* LE == (Z || (N!=V)) */
82 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); in kvm_condition_valid32()
108 * IT[7:0] -> CPSR[26:25],CPSR[15:10]
121 itbits |= (cpsr & (0x3 << 25)) >> 25; in kvm_adjust_itstate()
132 cpsr |= (itbits & 0x3) << 25; in kvm_adjust_itstate()
/linux-6.12.1/drivers/ata/
Dlibata-pata-timings.c31 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 },
32 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 },
41 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 },
42 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 },
43 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 },
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1) argument
58 #define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0) argument
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dmediatek,mt7621-pcie.yaml26 v
31 v v v On Bus0
39 On Bus1 v On Bus2 v On Bus3 v
129 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
155 resets = <&rstctrl 25>;
156 clocks = <&clkctrl 25>;
169 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
/linux-6.12.1/include/linux/spi/
Dmxs-spi.h24 #define BM_SSP_CTRL0_READ (1 << 25)
36 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
71 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
[all …]
/linux-6.12.1/drivers/hwmon/
Dabituguru3.c191 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
192 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
193 { "MCH 2.5V", 5, 0, 20, 1, 0 },
194 { "ICH 1.05V", 6, 0, 10, 1, 0 },
195 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
196 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
197 { "ATX +5V", 9, 0, 30, 1, 0 },
198 { "+3.3V", 10, 0, 20, 1, 0 },
201 { "System", 25, 1, 1, 1, 0 },
213 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
[all …]
/linux-6.12.1/include/linux/
Dinet.h12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
21 * $Id: ip.c,v 0.8.4.8 1992/12/12 19:25:04 bir7 Exp $
[all …]
/linux-6.12.1/tools/testing/selftests/hid/tests/
Dtest_tablet.py625 for v in self.parsed_rdesc.feature_reports.values():
626 if v.report_ID == rnum:
627 rdesc = v
639 for v in self.parsed_rdesc.feature_reports.values():
640 if v.report_ID == rnum:
641 rdesc = v
727 [pytest.param(v, id=k) for k, v in PenState.legal_transitions().items()],
740 pytest.param(v, id=k)
741 for k, v in PenState.tolerated_transitions().items()
758 pytest.param(v, id=k)
[all …]
/linux-6.12.1/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/linux-6.12.1/drivers/i3c/master/mipi-i3c-hci/
Dcmd_v1.c27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
46 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v) argument
[all …]
/linux-6.12.1/lib/crypto/
Dcurve25519-fiat32.c20 * fe limbs are bounded by 1.125*2^26,1.125*2^25,1.125*2^26,1.125*2^25,etc.
23 typedef struct fe { u32 v[10]; } fe; member
25 /* fe_loose limbs are bounded by 3.375*2^26,3.375*2^25,3.375*2^26,3.375*2^25,etc
28 typedef struct fe_loose { u32 v[10]; } fe_loose; member
42 h[1] = (a0>>26) | ((a1&((1<<19)-1))<< 6); /* (32-26) + 19 = 6+19 = 25 */ in fe_frombytes_impl()
44 h[3] = (a2>>13) | ((a3&((1<< 6)-1))<<19); /* (32-13) + 6 = 19+ 6 = 25 */ in fe_frombytes_impl()
46 h[5] = a4&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
47 h[6] = (a4>>25) | ((a5&((1<<19)-1))<< 7); /* (32-25) + 19 = 7+19 = 26 */ in fe_frombytes_impl()
48 h[7] = (a5>>19) | ((a6&((1<<12)-1))<<13); /* (32-19) + 12 = 13+12 = 25 */ in fe_frombytes_impl()
50 h[9] = (a7>> 6)&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
[all …]
/linux-6.12.1/drivers/media/platform/sunxi/sun6i-mipi-csi2/
Dsun6i_mipi_csi2_reg.h17 #define SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(v) ((((v) - 1) << 8) & \ argument
19 #define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v) (((v) - 1) & GENMASK(1, 0)) argument
36 #define SUN6I_MIPI_CSI2_CH_INT_EN_LINE_SYNC_ERR BIT(25)
53 #define SUN6I_MIPI_CSI2_CH_INT_PD_LINE_SYNC_ERR BIT(25)
/linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/
Dtc_sample.sh63 ip -4 route add default vrf v$h1 nexthop via 192.0.2.2
68 ip -4 route del default vrf v$h1 nexthop via 192.0.2.2
77 ip -4 route add default vrf v$h2 nexthop via 198.51.100.2
82 ip -4 route del default vrf v$h2 nexthop via 198.51.100.2
95 ip -4 route add default vrf v${h3}_bond nexthop via 192.0.2.18
100 ip -4 route del default vrf v${h3}_bond nexthop via 192.0.2.18
116 ip -4 route add default vrf v${h4}_bond nexthop via 198.51.100.18
121 ip -4 route del default vrf v${h4}_bond nexthop via 198.51.100.18
238 ip vrf exec v$h1 $MZ $h1 -c 320000 -d 100usec -p 64 -A 192.0.2.1 \
245 (( -25 <= pct && pct <= 25))
[all …]
/linux-6.12.1/drivers/clk/versatile/
Dclk-icst.c74 * bits of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
81 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
89 * access the low eight bits of the v PLL divider. Bit 8 is tied low in vco_get()
96 vco->v = val & INTEGRATOR_AP_SYS_BITS; in vco_get()
106 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the in vco_get()
107 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies in vco_get()
108 * 33 or 25 MHz respectively. in vco_get()
113 vco->v = divxy ? 17 : 14; in vco_get()
121 * of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
128 vco->v = val & 0xFF; in vco_get()
[all …]
/linux-6.12.1/drivers/net/hamradio/
Dbpqether.c3 * G8BPQ compatible "AX.25 via ethernet" driver release 004
7 * This is a "pseudo" network driver to allow AX.25 over Ethernet
15 * - user-level programs like the AX.25 utilities shouldn't
17 * - IP over ethernet encapsulated AX.25 was impossible
38 * BPQ 001 Joerg(DL1BKE) Extracted BPQ code from AX.25
85 "AX.25: bpqether driver version 004\n";
168 * Receive an AX.25 frame via an ethernet interface.
236 * Send an AX.25 frame via an ethernet interface
299 * Set AX.25 callsign
394 static void *bpq_seq_next(struct seq_file *seq, void *v, loff_t *pos) in bpq_seq_next() argument
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7091r5.yaml33 Provide VDD power to the sensor (VDD range is from 2.7V to 5.25V).
38 The V_drive voltage range is from 1.8V to 5.25V and must not exceed VDD by
39 more than 0.3V.
106 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
122 convst-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
/linux-6.12.1/drivers/net/wan/
DKconfig9 Wide Area Networks (WANs), such as X.25, Frame Relay and leased
37 Relay, synchronous Point-to-Point Protocol (PPP) and X.25.
88 tristate "X.25 protocol support"
91 Generic HDLC driver supporting X.25 over WAN connections.
95 comment "X.25/LAPB support is disabled"
185 Support for the FarSync T-Series X.21 (and V.35/V.24) cards by
189 8Mb/s (128K on V.24) using synchronous PPP, Cisco HDLC, raw HDLC,
190 Frame Relay or X.25/LAPB.
244 # X.25 network drivers
/linux-6.12.1/tools/testing/selftests/bpf/progs/
Diters.c34 int *v, i = zero; /* obscure initial value of i */ in iter_err_unsafe_c_loop() local
39 while ((v = bpf_iter_num_next(&it))) { in iter_err_unsafe_c_loop()
96 int *v; in iter_while_loop() local
101 while ((v = bpf_iter_num_next(&it))) { in iter_while_loop()
102 bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v); in iter_while_loop()
114 int *v; in iter_while_loop_auto_cleanup() local
119 while ((v = bpf_iter_num_next(&it))) { in iter_while_loop_auto_cleanup()
120 bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v); in iter_while_loop_auto_cleanup()
132 int *v; in iter_for_loop() local
137 for (v = bpf_iter_num_next(&it); v; v = bpf_iter_num_next(&it)) { in iter_for_loop()
[all …]
/linux-6.12.1/drivers/net/ethernet/altera/
Daltera_tse.h53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
73 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) argument
80 #define MAC_CMDCFG_ENA_10 BIT(25)
85 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) argument
86 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) argument
87 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) argument
88 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) argument
89 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) argument
90 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) argument
91 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) argument
[all …]

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