| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | motorcomm,yt8xxx.yaml | 26 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
28 default: 1950
35 1950, 2100, 2250 ]
36 default: 1950
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| /linux-6.12.1/Documentation/input/ |
| D | interactive.svg | 5 …<polyline transform="translate(-18.5,-16.294)" points="2400 4800 2400 6525 1950 7125 1950 7800" fi…
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| D | shape.svg | 26 …<polyline transform="translate(-121.88 -68.4)" points="8250 3150 8250 2475 8775 1950 8775 1200" fi…
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 217 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x in dcn32_init_clocks()
218 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950) in dcn32_init_clocks()
219 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950; in dcn32_init_clocks()
227 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x in dcn32_init_clocks()
228 if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950) in dcn32_init_clocks()
229 clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950; in dcn32_init_clocks()
244 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) in dcn32_init_clocks()
245 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950; in dcn32_init_clocks()
256 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 1950) in dcn32_init_clocks()
257 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz = 1950; in dcn32_init_clocks()
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| /linux-6.12.1/drivers/soc/tegra/fuse/ |
| D | speedo-tegra210.c | 46 { 1950, 2100, UINT_MAX },
47 { 1950, 2100, UINT_MAX },
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | sienna_cichlid_ppt.h | 36 #define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950
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| /linux-6.12.1/arch/sh/boards/mach-dreamcast/ |
| D | rtc.c | 16 /* The AICA RTC has an Epoch of 1/1/1950, so we must subtract 20 years (in
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| /linux-6.12.1/drivers/regulator/ |
| D | sy8106a-regulator.c | 40 #define SY8106A_MAX_MV 1950
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| /linux-6.12.1/tools/power/cpupower/debug/i386/ |
| D | dump_psb.c | 32 2000, 1950, 1900, 1850, 1800, 1750, 1700, 1650,
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| /linux-6.12.1/drivers/media/usb/pvrusb2/ |
| D | pvrusb2-devattr.h | 70 #define PVR2_IR_SCHEME_ZILOG 2 /* HVR-1950 style (must be taken out of reset) */
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| D | pvrusb2-devattr.c | 476 .description = "WinTV HVR-1950 Model 750xx",
499 .description = "WinTV HVR-1950 Model 751xx",
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| D | pvrusb2-i2c-core.c | 569 case PVR2_IR_SCHEME_ZILOG: /* HVR-1950 style */ in pvr2_i2c_register_ir()
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| /linux-6.12.1/Documentation/RCU/Design/Data-Structures/ |
| D | blkd_task.svg | 557 width="1950"
566 width="1950"
575 width="1950"
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| D | TreeMappingLevel.svg | 259 y="1950"
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| /linux-6.12.1/drivers/media/dvb-frontends/ |
| D | stb6000.c | 91 if (freq_mhz < 1950) in stb6000_set_params()
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| /linux-6.12.1/arch/x86/pci/ |
| D | common.c | 251 .ident = "Dell PowerEdge 1950",
254 DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
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| /linux-6.12.1/drivers/mmc/core/ |
| D | regulator.c | 43 *max_uV = 1950 * 1000; in mmc_ocrbitnum_to_vdd()
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| /linux-6.12.1/Documentation/userspace-api/media/v4l/ |
| D | constraints.svg | 10 …="550" width="601" height="1451" fill="none"/><path id="path310" d="m9837 1950v-1453" fill="none" …
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| D | mt2110t.svg | 101 … <path fill="rgb(0,0,0)" stroke="none" d="M 13446,1650 L 13346,1950 13546,1950 13446,1650 Z"/>
302 <path fill="none" stroke="rgb(0,0,0)" d="M 12443,2163 L 12443,1950"/>
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| /linux-6.12.1/include/linux/ |
| D | zlib.h | 26 Comments) 1950 to 1952 in the files https://www.ietf.org/rfc/rfc1950.txt
66 the zlib format, which is a zlib wrapper documented in RFC 1950, wrapped
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| /linux-6.12.1/drivers/infiniband/hw/hns/ |
| D | hns_roce_hw_v2.h | 638 #define QPC_LCL_OP_FLG QPC_FIELD_LOC(1950, 1950)
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| /linux-6.12.1/drivers/cpufreq/ |
| D | powernow-k7.c | 71 2000, 1950, 1900, 1850, 1800, 1750, 1700, 1650,
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| /linux-6.12.1/drivers/media/pci/intel/ipu6/ |
| D | ipu6-isys-dwc-phy.c | 275 {0x3f, 1841, 2060, 1950, 261},
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| /linux-6.12.1/drivers/leds/ |
| D | leds-lm3532.c | 214 2310, 2180, 2060, 1950,
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| /linux-6.12.1/drivers/net/phy/ |
| D | motorcomm.c | 802 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
820 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS },
859 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, in ytphy_get_delay_reg_value()
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