Searched +full:0 +full:xffe00000 (Results 1 – 25 of 93) sorted by relevance
1234
| /linux-6.12.1/Documentation/devicetree/bindings/timer/ |
| D | snps,dw-apb-timer.yaml | 64 interrupts = <0 170 4>;
65 reg = <0xffe00000 0x1000>;
72 interrupts = <0 170 4>;
73 reg = <0xffe00000 0x1000>;
80 interrupts = <0 170 4>;
81 reg = <0xffe00000 0x1000>;
|
| /linux-6.12.1/net/netfilter/ipset/ |
| D | pfxlen.c | 12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
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| /linux-6.12.1/arch/sh/kernel/cpu/sh4a/ |
| D | serial-sh7722.c | 6 #define PSCR 0xA405011E
12 if (port->mapbase == 0xffe00000) { in sh7722_sci_init_pins()
14 data &= ~0x03cf; in sh7722_sci_init_pins()
16 data |= 0x0340; in sh7722_sci_init_pins()
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| /linux-6.12.1/arch/parisc/kernel/ |
| D | perf_images.h | 27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
| D | p1020rdb_36b.dts | 18 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb00000 0x00020000>;
27 ranges = <0x0 0xf 0xffe00000 0x100000>;
31 reg = <0xf 0xffe09000 0 0x1000>;
32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xc0000000
[all …]
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| D | p1020rdb.dts | 18 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
33 reg = <0 0xffe09000 0 0x1000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xa0000000
[all …]
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| D | mpc8572ds_36b.dts | 19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
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| D | mpc8572ds.dts | 19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
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| D | p2020ds.dts | 19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
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| D | mpc8536ds_36b.dts | 17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
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| D | mpc8536ds.dts | 17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 0x2 0x0 0x0 0xffa00000 0x00040000
36 0x3 0x0 0x0 0xffdf0000 0x00008000>;
40 ranges = <0x0 0 0xffe00000 0x100000>;
44 reg = <0 0xffe08000 0 0x1000>;
[all …]
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| D | p1024rdb_36b.dts | 45 reg = <0xf 0xffe05000 0 0x1000>;
46 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
47 0x1 0x0 0xf 0xff800000 0x00040000>;
51 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 reg = <0xf 0xffe09000 0 0x1000>;
56 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
57 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
58 pcie@0 {
59 ranges = <0x2000000 0x0 0xe0000000
60 0x2000000 0x0 0xe0000000
[all …]
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| D | p1024rdb_32b.dts | 45 reg = <0x0 0xffe05000 0 0x1000>;
46 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
47 0x1 0x0 0x0 0xff800000 0x00040000>;
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
55 reg = <0x0 0xffe09000 0 0x1000>;
56 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
57 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
58 pcie@0 {
59 ranges = <0x2000000 0x0 0xe0000000
60 0x2000000 0x0 0xe0000000
[all …]
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| D | p1010rdb_32b.dtsi | 41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
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| D | p1010rdb_36b.dtsi | 41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
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| D | p1021rdb-pc_36b.dts | 45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 reg = <0xf 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
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| D | p1021rdb-pc_32b.dts | 45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
60 reg = <0 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
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| D | p2020rdb-pc_36b.dts | 46 reg = <0xf 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
50 0x1 0x0 0xf 0xff800000 0x00040000
51 0x2 0x0 0xf 0xffb00000 0x00020000
52 0x3 0x0 0xf 0xffa00000 0x00020000>;
56 ranges = <0x0 0xf 0xffe00000 0x100000>;
60 reg = <0xf 0xffe08000 0 0x1000>;
65 reg = <0xf 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
[all …]
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| D | p2020rdb-pc_32b.dts | 46 reg = <0 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
50 0x1 0x0 0x0 0xff800000 0x00040000
51 0x2 0x0 0x0 0xffb00000 0x00020000
52 0x3 0x0 0x0 0xffa00000 0x00020000>;
56 ranges = <0x0 0x0 0xffe00000 0x100000>;
60 reg = <0 0xffe08000 0 0x1000>;
65 reg = <0 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
[all …]
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| D | p1025twr.dts | 45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x2 0x0 0x0 0xe0000000 0x00020000>;
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xa0000000
62 0x2000000 0x0 0xa0000000
[all …]
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| D | p1020rdb-pc_32b.dts | 45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000
51 0x3 0x0 0x0 0xffa00000 0x00020000>;
55 ranges = <0x0 0x0 0xffe00000 0x100000>;
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
61 reg = <0 0xffe09000 0 0x1000>;
62 pcie@0 {
[all …]
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| D | p1020rdb-pc_36b.dts | 45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00040000
51 0x3 0x0 0xf 0xffa00000 0x00020000>;
55 ranges = <0x0 0xf 0xffe00000 0x100000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
61 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
62 pcie@0 {
[all …]
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| D | p1020utm-pc_32b.dts | 45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x02000000
49 0x1 0x0 0x0 0xffa00000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 reg = <0x0 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
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| /linux-6.12.1/arch/x86/include/uapi/asm/ |
| D | e820.h | 4 #define E820MAP 0x2d0 /* our map */
29 #define E820NR 0x1e8 /* # entries in E820MAP */
70 #define ISA_START_ADDRESS 0xa0000
71 #define ISA_END_ADDRESS 0x100000
73 #define BIOS_BEGIN 0x000a0000
74 #define BIOS_END 0x00100000
76 #define BIOS_ROM_BASE 0xffe00000
77 #define BIOS_ROM_END 0xffffffff
|
| /linux-6.12.1/Documentation/devicetree/bindings/remoteproc/ |
| D | xlnx,zynqmp-r5fss.yaml | 39 enum: [0, 1, 2]
44 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
47 If set to 1 then lockstep mode and if 0 then split mode.
50 0: split mode
56 enum: [0, 1]
59 0: split mode
63 "^r(.*)@[0-9a-f]+$":
162 "^r52f@[0-9a-f]+$":
206 "^r5f@[0-9a-f]+$":
241 enum: [0]
[all …]
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