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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drockchip,pcie3-phy.yaml31 controller (value). 0 means lane disabled, higher value means used.
37 minimum: 0
41 const: 0
59 RX common reference clock mode. 0 means disabled, 1 means enabled.
64 minimum: 0
104 reg = <0xfe8c0000 0x20000>;
105 #phy-cells = <0>;
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi13 reg = <0 0xfc000000 0 0x1000>;
20 ports-implemented = <0x1>;
27 reg = <0x0 0xfdc70000 0x0 0x1000>;
32 reg = <0x0 0xfe190080 0x0 0x20>;
37 reg = <0x0 0xfe190100 0x0 0x20>;
42 reg = <0x0 0xfe190200 0x0 0x20>;
47 reg = <0x0 0xfdcb8000 0x0 0x10000>;
52 reg = <0x0 0xfe8c0000 0x0 0x20000>;
53 #phy-cells = <0>;
67 bus-range = <0x0 0xf>;
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