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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dxlnx,zynqmp-psgtr.yaml24 minimum: 0
34 minimum: 0
38 minimum: 0
50 Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
57 pattern: "^ref[0-3]$"
97 reg = <0xfd400000 0x40000>,
98 <0xfd3d0000 0x1000>;
100 clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
/linux-6.12.1/arch/arm64/boot/dts/lg/
Dlg1313.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
Dlg1312.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/
Dgaudi2_special_blocks.h16 { GAUDI2_BLOCK_TYPE_TPC, 0xfc008000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
17 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00a000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
18 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00b000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
19 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00c000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
20 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc080000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
21 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc081000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
22 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc083000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
23 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc084000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
24 { GAUDI2_BLOCK_TYPE_MME, 0xfc0c8000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
25 { GAUDI2_BLOCK_TYPE_MME, 0xfc0c9000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
[all …]
/linux-6.12.1/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi30 bootscr-address = /bits/ 64 <0x20000000>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
43 reg = <0x0>;
52 reg = <0x1>;
62 reg = <0x2>;
72 reg = <0x3>;
87 CPU_SLEEP_0: cpu-sleep-0 {
89 arm,psci-suspend-param = <0x40000000>;
130 reg = <0x0 0x3ed00000 0x0 0x40000>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
60 i-cache-size = <0x8000>;
63 d-cache-size = <0x8000>;
72 reg = <0x0 0x100>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
88 reg = <0x0 0x200>;
[all …]