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/linux-6.12.1/Documentation/devicetree/bindings/timer/
Drenesas,mtu2.yaml18 independent. The MTU2 hardware supports five channels indexed from 0 to 4.
70 reg = <0xfcff0000 0x400>;
/linux-6.12.1/drivers/net/ethernet/ti/icssg/
Dicssg_config.c21 #define MII_RT_TX_IPG_100M 0x17
22 #define MII_RT_TX_IPG_1G 0xb
23 #define MII_RT_TX_IPG_100M_SR1 0x166
24 #define MII_RT_TX_IPG_1G_SR1 0x1a
27 #define ICSSG_QUEUE_OFFSET 0xd00
28 #define ICSSG_QUEUE_PEEK_OFFSET 0xe00
29 #define ICSSG_QUEUE_CNT_OFFSET 0xe40
30 #define ICSSG_QUEUE_RESET_OFFSET 0xf40
66 #define FDB_GEN_CFG1 0x60
70 #define FDB_GEN_CFG2 0x64
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr7s72100.dtsi32 #clock-cells = <0>;
43 ranges = <0 0 0x18000000>;
48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0>;
62 #clock-cells = <0>;
65 clock-frequency = <0>;
69 #clock-cells = <0>;
77 #clock-cells = <0>;
86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/linux-6.12.1/arch/parisc/kernel/
Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]