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/linux-6.12.1/drivers/gpu/drm/etnaviv/
Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
Dmvme7100.dts18 reg = <0x00000000 0x80000000>;
22 ranges = <0x00000000 0xf1000000 0x00100000>;
27 reg = <0x4c>;
89 reg = <0xf1005000 0x1000>;
91 ranges = <0 0 0xf8000000 0x08000000 // NOR Flash (128MB)
92 2 0 0xf2030000 0x00010000 // NAND Flash (8GB)
93 3 0 0xf2400000 0x00080000 // MRAM (512KB)
94 4 0 0xf2000000 0x00010000 // BCSR
95 5 0 0xf2010000 0x00010000>; // QUART
97 bcsr@4,0 {
[all …]
Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/linux-6.12.1/arch/arm/include/debug/
Dsa1100.S10 #define UTCR3 0x0c
11 #define UTDR 0x14
12 #define UTSR1 0x20
13 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
14 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
15 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
18 mrc p15, 0, \rp, c1, c0
20 moveq \rp, #0x80000000 @ physical base address
21 movne \rp, #0xf8000000 @ virtual address
28 add \rp, \rp, #0x00050000
[all …]
Dvt8500.S10 #define DEBUG_LL_PHYS_BASE 0xD8000000
11 #define DEBUG_LL_VIRT_BASE 0xF8000000
12 #define DEBUG_LL_UART_OFFSET 0x00200000
22 strb \rd, [\rx, #0]
26 1001: ldr \rd, [\rx, #0x1c]
27 ands \rd, \rd, #0x2
Dvexpress.S10 #define DEBUG_LL_PHYS_BASE 0x10000000
11 #define DEBUG_LL_UART_OFFSET 0x00009000
13 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
14 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
16 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
18 #define DEBUG_LL_VIRT_BASE 0xf8000000
27 @ should use UART at 0x10009000
29 @ at 0x1c090000
30 mrc p15, 0, \rp, c0, c0, 0
31 movw \rv, #0xc091
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/linux-6.12.1/net/netfilter/ipset/
Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux-6.12.1/Documentation/arch/x86/
Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
96 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
107 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dbrcm,stb-pcie.yaml190 reg = <0x0 0x7d500000 0x9310>;
198 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
199 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
200 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
201 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
202 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
206 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
207 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
208 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
210 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
[all …]
Drockchip,rk3399-pcie.yaml61 const: 0
98 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
99 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
100 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
103 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
104 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
106 msi-map = <0x0 &its 0x0 0x1000>;
107 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
118 pinctrl-0 = <&pcie_clkreq>;
120 interrupt-map-mask = <0 0 0 7>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/board/
Dfsl,bcsr.yaml30 reg = <0xf8000000 0x8000>;
/linux-6.12.1/sound/isa/gus/
Dgus_volume.c24 while (e > 0 && tmp < (1 << e)) in snd_gf1_lvol_to_gvol_raw()
33 if (m > 0) { in snd_gf1_lvol_to_gvol_raw()
43 #if 0
51 return 0;
81 vol_rates[0] :
83 for (i = 0; i < 3; i++) {
95 return (range << 6) | (increment & 0x3f);
98 #endif /* 0 */
105 if (freq16 & 0xf8000000) { in snd_gf1_translate_freq()
106 freq16 = ~0xf8000000; in snd_gf1_translate_freq()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Dhisilicon,hi655x.txt19 - #clock-cells: From common clock binding; shall be set to 0
28 reg = <0x0 0xf8000000 0x0 0x1000>;
32 #clock-cells = <0>;
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dartpec6.txt30 #clock-cells = <0>;
38 reg = <0xf8000000 0x48>;
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91sam9x5_can.dtsi17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/linux-6.12.1/arch/arm/mach-sa1100/include/mach/
Dhardware.h17 #define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
31 #define VIO_BASE 0xf8000000 /* virtual start of IO space */
33 #define PIO_START 0x80000000 /* physical start of IO space */
36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
38 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
/linux-6.12.1/arch/arm/boot/dts/st/
Dspear600-evb.dts17 reg = <0 0x10000000>;
55 reg = <0xf8000000 0x800000>;
63 partition@0 {
65 reg = <0x0 0x10000>;
69 reg = <0x10000 0x50000>;
73 reg = <0x60000 0x10000>;
77 reg = <0x70000 0x10000>;
81 reg = <0x80000 0x310000>;
85 reg = <0x390000 0x0>;
Dspear310-evb.dts18 reg = <0 0x40000000>;
24 pinctrl-0 = <&state_default>;
102 reg = <0xf8000000 0x800000>;
105 partition@0 {
107 reg = <0x0 0x10000>;
111 reg = <0x10000 0x50000>;
115 reg = <0x60000 0x10000>;
119 reg = <0x70000 0x10000>;
123 reg = <0x80000 0x310000>;
127 reg = <0x390000 0x0>;
[all …]
Dspear320-evb.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
103 reg = <0xf8000000 0x800000>;
106 partition@0 {
108 reg = <0x0 0x10000>;
112 reg = <0x10000 0x50000>;
116 reg = <0x60000 0x10000>;
120 reg = <0x70000 0x10000>;
124 reg = <0x80000 0x310000>;
128 reg = <0x390000 0x0>;
[all …]
Dspear300-evb.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
77 cd-gpios = <&gpio1 0 0>;
88 reg = <0xf8000000 0x800000>;
91 partition@0 {
93 reg = <0x0 0x10000>;
97 reg = <0x10000 0x50000>;
101 reg = <0x60000 0x10000>;
105 reg = <0x70000 0x10000>;
109 reg = <0x80000 0x310000>;
[all …]
/linux-6.12.1/arch/arm/mach-pxa/
Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/linux-6.12.1/sound/pci/hda/
Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/linux-6.12.1/arch/powerpc/platforms/chrp/
Dgg2.h23 #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
26 #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */
27 #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */
29 #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */
30 #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */
39 #define GG2_PCI_BUSNO 0x40 /* Bus number */
40 #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */
41 #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */
[all …]

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