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/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.yaml154 reg = <0xff000000 0x01000000>;
160 ranges = <0 0xff000000 0x01000000>;
162 fs@0 {
164 reg = <0 0xf80000>;
168 reg = <0xf80000 0x80000>;
176 flash@0 {
178 reg = <0x00000000 0x02000000>,
179 <0x02000000 0x02000000>;
184 ranges = <0 0 0x04000000>;
186 partition@0 {
[all …]
/linux-6.12.1/include/rdma/
Dopa_addr.h11 #define OPA_SPECIAL_OUI (0x00066AULL)
14 ? 0 : x)
15 #define OPA_GID_INDEX 0x1
17 * 0xF8 - 4 bits of multicast range and 1 bit for collective range
19 * Multicast range: 0xF00000 to 0xF7FFFF
20 * Collective range: 0xF80000 to 0xFFFFFE
22 #define OPA_MCAST_NR 0x4 /* Number of top bits set */
23 #define OPA_COLLECTIVE_NR 0x1 /* Number of bits after MCAST_NR */
48 return be64_to_cpu(gid->global.interface_id) & 0xFFFFFFFF; in opa_get_lid_from_gid()
/linux-6.12.1/drivers/mtd/maps/
Dnetsc520.c45 .offset = 0,
46 .size = 0xc0000
50 .offset = 0xc0000,
51 .size = 0x40000
55 .offset = 0x100000,
56 .size = 0xe80000
60 .offset = 0xf80000,
61 .size = 0x80000
66 #define WINDOW_SIZE 0x00100000
67 #define WINDOW_ADDR 0x00200000
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2l-evm.dts23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
33 #clock-cells = <0>;
56 reg = <0x50>;
67 ti,cs-chipselect = <0>;
77 nand@0,0 {
81 reg = <0 0 0x4000000
82 1 0 0x0000100>;
84 ti,davinci-chipselect = <0>;
85 ti,davinci-mask-ale = <0x2000>;
86 ti,davinci-mask-cle = <0x4000>;
[all …]
Dkeystone-k2e-evm.dts23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #clock-cells = <0>;
83 reg = <0x50>;
94 ti,cs-chipselect = <0>;
104 nand@0,0 {
108 reg = <0 0 0x4000000
109 1 0 0x0000100>;
111 ti,davinci-chipselect = <0>;
[all …]
Dkeystone-k2hk-evm.dts23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
111 ti,cs-chipselect = <0>;
121 nand@0,0 {
125 reg = <0 0 0x4000000
126 1 0 0x0000100>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
/linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/
Drcar_du_plane.c75 return 0; in rcar_du_plane_hwmask()
86 * VSPD1. VSPD0 feeds DU0/1 plane 0, and VSPD1 feeds either DU2 plane 0 or
91 * availability of planes 0 and 1.
105 /* VSPD0 feeds plane 0 on DU0/1. */ in rcar_du_plane_hwalloc()
106 if (plane->group->index != 0) in rcar_du_plane_hwalloc()
109 fixed = 0; in rcar_du_plane_hwalloc()
111 /* VSPD1 feeds plane 1 on DU0/1 or plane 0 on DU2. */ in rcar_du_plane_hwalloc()
112 fixed = plane->group->index == 0 ? 1 : 0; in rcar_du_plane_hwalloc()
115 if (fixed >= 0) in rcar_du_plane_hwalloc()
118 for (i = RCAR_DU_NUM_HW_PLANES - 1; i >= 0; --i) { in rcar_du_plane_hwalloc()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-sm-k26-revA.dts50 memory@0 {
52 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
61 reg = <0x0 0x7ff00000 0x0 0x100000>;
95 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
110 pwms = <&ttc0 2 40000 0>;
144 &qspi { /* MIO 0-5 - U143 */
146 spi_flash: flash@0 { /* MT25QU512A */
148 reg = <0>;
158 partition@0 {
160 reg = <0x0 0x80000>; /* 512KB */
[all …]
/linux-6.12.1/drivers/net/ethernet/myricom/myri10ge/
Dmyri10ge_mcp.h54 #define MXGEFW_FLAGS_SMALL 0x1
55 #define MXGEFW_FLAGS_TSO_HDR 0x1
56 #define MXGEFW_FLAGS_FIRST 0x2
57 #define MXGEFW_FLAGS_ALIGN_ODD 0x4
58 #define MXGEFW_FLAGS_CKSUM 0x8
59 #define MXGEFW_FLAGS_TSO_LAST 0x8
60 #define MXGEFW_FLAGS_NO_TSO 0x10
61 #define MXGEFW_FLAGS_TSO_CHOP 0x10
62 #define MXGEFW_FLAGS_TSO_PLD 0x20
95 #define MXGEFW_BOOT_HANDOFF 0xfc0000
[all …]
/linux-6.12.1/drivers/cpufreq/
Dti-cpufreq.c21 #define REVISION_MASK 0xF
24 #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
25 #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
33 #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
38 #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
39 #define OMAP3_CONTROL_IDCODE 0x4830A204
40 #define OMAP34xx_ProdID_SKUID 0x4830A20C
41 #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
47 #define AM625_SUPPORT_K_MPU_OPP BIT(0)
69 #define AM62A7_SUPPORT_N_MPU_OPP BIT(0)
[all …]
/linux-6.12.1/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39 * 3. RF register 0x00-2E
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
47 #define rPMAC_TxStart 0x104
48 #define rPMAC_TxLegacySIG 0x108
49 #define rPMAC_TxHTSIG1 0x10c
50 #define rPMAC_TxHTSIG2 0x110
51 #define rPMAC_PHYDebug 0x114
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/dispnv04/
Dcrtc.c71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
85 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ in nv_crtc_set_image_sharpening()
86 level += 0x40; in nv_crtc_set_image_sharpening()
103 /* NV4x 0x40.. pll notes:
104 * gpu pll: 0x4000 + 0x4004
105 * ?gpu? pll: 0x4008 + 0x400c
106 * vpll1: 0x4010 + 0x4014
107 * vpll2: 0x4018 + 0x401c
108 * mpll: 0x4020 + 0x4024
109 * mpll: 0x4038 + 0x403c
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_SYS_SWR_CTRL1 0x0010
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]

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