Searched +full:0 +full:xf0000 (Results 1 – 25 of 180) sorted by relevance
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27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x236 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1[all …]
27 #define IH_VMID_0_LUT__PASID_MASK 0xffff28 #define IH_VMID_0_LUT__PASID__SHIFT 0x029 #define IH_VMID_1_LUT__PASID_MASK 0xffff30 #define IH_VMID_1_LUT__PASID__SHIFT 0x031 #define IH_VMID_2_LUT__PASID_MASK 0xffff32 #define IH_VMID_2_LUT__PASID__SHIFT 0x033 #define IH_VMID_3_LUT__PASID_MASK 0xffff34 #define IH_VMID_3_LUT__PASID__SHIFT 0x035 #define IH_VMID_4_LUT__PASID_MASK 0xffff36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0[all …]
23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 024 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 024 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 024 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 032 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 024 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
10 #define RF_DATA 0x1d412 #define rPMAC_Reset 0x10013 #define rPMAC_TxStart 0x10414 #define rPMAC_TxLegacySIG 0x10815 #define rPMAC_TxHTSIG1 0x10c16 #define rPMAC_TxHTSIG2 0x11017 #define rPMAC_PHYDebug 0x11418 #define rPMAC_TxPacketNum 0x11819 #define rPMAC_TxIdle 0x11c20 #define rPMAC_TxMACHeader0 0x120[all …]
23 memory@0 {25 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;35 gpios-states = <0>;36 states = <1800000 0x137 3300000 0x0>;81 flash@0 {82 reg = <0>;91 partition@0 {93 reg = <0 0xf0000>;98 reg = <0xf0000 0x8000>;[all …]
24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F029 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400034 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F039 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0041 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000[all …]
24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F029 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400034 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F039 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0041 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000[all …]
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1036 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4[all …]
14 #define CCSC00_OFFSET 0xAA05015 #define CCSC01_OFFSET 0xFA05016 #define CCSC01_D1_OFFSET 0xFA00017 #define CCSC10_OFFSET 0xA000018 #define CCSC11_OFFSET 0xF000020 #define SUN8I_CSC_CTRL(base) ((base) + 0x0)21 #define SUN8I_CSC_COEFF(base, i) ((base) + 0x10 + 4 * (i))23 #define SUN8I_CSC_CTRL_EN BIT(0)
19 reg = <0x18000 0x20>;24 reg = <0xa8000 0x2000>;32 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
3 * QorIQ FMan v3 10g port #0 device tree11 cell-index = <0x10>;13 reg = <0x90000 0x1000>;18 cell-index = <0x30>;20 reg = <0xb0000 0x1000>;25 cell-index = <0x8>;27 reg = <0xf0000 0x1000>;35 #size-cells = <0>;37 reg = <0xf1000 0x1000>;39 pcsphy6: ethernet-phy@0 {[all …]
27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x029 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x031 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x033 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x3034 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x435 #define UVD_SEMA_CMD__MODE_MASK 0x4036 #define UVD_SEMA_CMD__MODE__SHIFT 0x6[all …]
12 u-boot@0 {13 reg = <0x0 0xe0000>;21 reg = <0xe0000 0x10000>;30 reg = <0xf0000 0x10000>;38 reg = <0x100000 0x7700000>;47 reg = <0x7800000 0x800000>;56 flash0@0 {57 reg = <0x0 0x8000000>;
8 PR_STS_SUCCESS = 0x0,14 PR_STS_IOERR = 0x2,15 PR_STS_RESERVATION_CONFLICT = 0x18,17 PR_STS_RETRY_PATH_FAILURE = 0xe0000,19 PR_STS_PATH_FAST_FAILED = 0xf0000,21 PR_STS_PATH_FAILED = 0x10000,59 #define PR_FL_IGNORE_KEY (1 << 0) /* ignore existing key */
15 memory@0 {17 reg = <0x0 0x8000000>;31 flash@0 {33 reg = <0>;41 partition@0 {43 reg = <0x0 0xe0000>;48 reg = <0xe0000 0x10000>;52 reg = <0xf0000 0x10000>;57 reg = <0x100000 0x100000>;61 reg = <0x200000 0x100000>;[all …]
12 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */13 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */14 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */15 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */17 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */18 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */20 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */21 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */22 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */23 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x836 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3[all …]
10 EFA_REGS_RESET_NORMAL = 0,24 /* 0 base */25 #define EFA_REGS_VERSION_OFF 0x026 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x427 #define EFA_REGS_CAPS_OFF 0x828 #define EFA_REGS_AQ_BASE_LO_OFF 0x1029 #define EFA_REGS_AQ_BASE_HI_OFF 0x1430 #define EFA_REGS_AQ_CAPS_OFF 0x1831 #define EFA_REGS_ACQ_BASE_LO_OFF 0x2032 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24[all …]