Searched +full:0 +full:xe000000 (Results 1 – 25 of 26) sorted by relevance
12
5 #define KERNBASE 0xE000000 /* First address the kernel will eventually be */6 #define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */
23 #define MME_ARCH_STATUS_A_SHIFT 024 #define MME_ARCH_STATUS_A_MASK 0x126 #define MME_ARCH_STATUS_B_MASK 0x228 #define MME_ARCH_STATUS_CIN_MASK 0x430 #define MME_ARCH_STATUS_COUT_MASK 0x832 #define MME_ARCH_STATUS_TE_MASK 0x1034 #define MME_ARCH_STATUS_LD_MASK 0x2036 #define MME_ARCH_STATUS_ST_MASK 0x4038 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x8040 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100[all …]
74 first child APLIC domain assigned child index 0. The APLIC domain child122 reg = <0xc000000 0x4080>;134 reg = <0xd000000 0x4080>;144 reg = <0xe000000 0x4080>;156 reg = <0xc000000 0x4000>;167 reg = <0xd000000 0x4000>;
10 #define RF_DATA 0x1d412 #define rPMAC_Reset 0x10013 #define rPMAC_TxStart 0x10414 #define rPMAC_TxLegacySIG 0x10815 #define rPMAC_TxHTSIG1 0x10c16 #define rPMAC_TxHTSIG2 0x11017 #define rPMAC_PHYDebug 0x11418 #define rPMAC_TxPacketNum 0x11819 #define rPMAC_TxIdle 0x11c20 #define rPMAC_TxMACHeader0 0x120[all …]
11 #define FSL_XCVR_MODE_SPDIF 016 #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */17 #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */23 #define FSL_XCVR_RX_FIFO_ADDR 0x0C0024 #define FSL_XCVR_TX_FIFO_ADDR 0x0E0026 #define FSL_XCVR_VERSION 0x00 /* Version */27 #define FSL_XCVR_EXT_CTRL 0x10 /* Control */28 #define FSL_XCVR_EXT_STATUS 0x20 /* Status */29 #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */30 #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */[all …]
36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE0039 * 3. RF register 0x00-2E44 * 1. Page1(0x100)46 #define rPMAC_Reset 0x10047 #define rPMAC_TxStart 0x10448 #define rPMAC_TxLegacySIG 0x10849 #define rPMAC_TxHTSIG1 0x10c50 #define rPMAC_TxHTSIG2 0x11051 #define rPMAC_PHYDebug 0x114[all …]
27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x128 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x029 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x230 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x131 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x432 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x233 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x834 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x335 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x1036 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4[all …]
7 #define REG_SYS_ISO_CTRL 0x00008 #define REG_SYS_FUNC_EN 0x00029 #define REG_APS_FSMCO 0x000410 #define REG_SYS_CLKR 0x000811 #define REG_9346CR 0x000A12 #define REG_EE_VPD 0x000C13 #define REG_AFE_MISC 0x001014 #define REG_SPS0_CTRL 0x001115 #define REG_SPS_OCP_CFG 0x001816 #define REG_RSV_CTRL 0x001C[all …]
7 #define TXPKT_BUF_SELECT 0x698 #define RXPKT_BUF_SELECT 0xA59 #define DISABLE_TRXPKT_BUF_ACCESS 0x011 #define REG_SYS_ISO_CTRL 0x000012 #define REG_SYS_FUNC_EN 0x000213 #define REG_APS_FSMCO 0x000414 #define REG_SYS_CLKR 0x000815 #define REG_9346CR 0x000A16 #define REG_EE_VPD 0x000C17 #define REG_SYS_SWR_CTRL1 0x0010[all …]
7 #define TXPKT_BUF_SELECT 0x698 #define RXPKT_BUF_SELECT 0xA59 #define DISABLE_TRXPKT_BUF_ACCESS 0x011 #define REG_SYS_ISO_CTRL 0x000012 #define REG_SYS_FUNC_EN 0x000213 #define REG_APS_FSMCO 0x000414 #define REG_SYS_CLKR 0x000815 #define REG_9346CR 0x000A16 #define REG_EE_VPD 0x000C17 #define REG_AFE_MISC 0x0010[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x00 0x70000000 0x00 0x200000>;25 ranges = <0x0 0x00 0x70000000 0x200000>;28 reg = <0x1c0000 0x20000>;32 reg = <0x1e0000 0x1c000>;36 reg = <0x1fc000 0x4000>;43 reg = <0x0 0x43000000 0x0 0x20000>;46 ranges = <0x0 0x0 0x43000000 0x20000>;51 reg = <0x00000014 0x4>;[all …]
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1036 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4[all …]
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x3036 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4[all …]
27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x029 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x031 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x033 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x10034 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x835 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x20036 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x836 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x136 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0[all …]
27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x128 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x029 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x130 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x031 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x033 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x300000034 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x1835 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x1000000036 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c[all …]