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/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-7040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
33 regulator-name = "cp0-usb3-0-current-regulator";
38 states = <500000 0x0
39 900000 0x1>;
41 gpios-states = <0>;
51 states = <500000 0x0
52 900000 0x1>;
54 gpios-states = <0>;
57 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
[all …]
Dcn9130-db.dtsi28 memory@0 {
30 reg = <0x0 0x0 0x0 0x80000000>;
39 states = <1800000 0x1 3300000 0x0>;
48 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
76 states = <1800000 0x1
77 3300000 0x0>;
131 phys = <&cp0_comphy4 0>;
161 pinctrl-0 = <&cp0_i2c0_pins>;
170 reg = <0x21>;
177 reg = <0x50>;
[all …]
Dcn9131-db.dtsi24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
45 pinctrl-0 = <&cp1_sfp_pins>;
61 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
90 phys = <&cp1_comphy4 0>;
106 pinctrl-0 = <&cp1_i2c0_pins>;
113 pinctrl-0 = <&cp1_pcie_reset_pins>;
116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
119 phys = <&cp1_comphy0 0
120 &cp1_comphy1 0>;
[all …]
Darmada-8040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
75 flash@0 {
77 reg = <0>;
[all …]
Dcn9130-crb.dtsi24 memory@0 {
26 reg = <0x0 0x0 0x0 0x80000000>;
35 states = <1800000 0x1
36 3300000 0x0>;
63 states = <1800000 0x1
64 3300000 0x0>;
105 cp0_i2c0_pins: cp0-i2c-pins-0 {
117 cp0_sdhci_pins: cp0-sdhi-pins-0 {
139 pinctrl-0 = <&cp0_i2c0_pins>;
146 reg = <0x20>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mtd/partitions/
Dnvmem-cells.yaml45 reg = <0x1200000 0x0140000>;
51 macaddr_gmac1: macaddr_gmac1@0 {
52 reg = <0x0 0x6>;
56 reg = <0x6 0x6>;
60 reg = <0x1000 0x2f20>;
64 reg = <0x5000 0x2f20>;
73 partition@0 {
75 reg = <0x000000 0x100000>;
82 reg = <0x100000 0xe00000>;
88 reg = <0xf00000 0x100000>;
[all …]
Dfixed-partitions.yaml51 "@[0-9a-f]+$":
77 partition@0 {
79 reg = <0x0000000 0x100000>;
84 reg = <0x0100000 0x200000>;
96 partition@0 {
98 reg = <0x00000000 0x1 0x00000000>;
110 partition@0 {
112 reg = <0x0 0x00000000 0x2 0x00000000>;
118 reg = <0x2 0x00000000 0x1 0x00000000>;
128 partition@0 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dti,k3-m4f-rproc.yaml92 reg = <0x00 0x9cb00000 0x00 0x100000>;
98 reg = <0x00 0x9cc00000 0x00 0xe00000>;
107 mailbox0_cluster0: mailbox-0 {
113 reg = <0x00 0x5000000 0x00 0x30000>,
114 <0x00 0x5040000 0x00 0x10000>;
123 ti,sci-proc-ids = <0x18 0xff>;
/linux-6.12.1/arch/mips/boot/dts/mobileye/
Deyeq5.dtsi15 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
34 reg = <0x8 0x04000000 0x0 0x1000000>;
37 reg = <0x8 0x05000000 0x0 0x1000000>;
40 reg = <0x8 0x06000000 0x0 0x100000>;
43 reg = <0x8 0x06100000 0x0 0x100000>;
47 reg = <0x8 0x06200000 0x0 0x100000>;
49 mhm_reserved_0: the-mhm-reserved-0@0 {
50 reg = <0x8 0x00000000 0x0 0x0000800>;
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-hdmi.c25 /* REG: 0x00 */
26 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
27 /* REG: 0x01 */
30 #define RK3228_BYPASS_PLLPD_EN BIT(0)
31 /* REG: 0x02 */
33 #define RK3228_PDATAEN_DISABLE BIT(0)
34 /* REG: 0x03 */
36 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
37 /* REG: 0x04 */
38 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x10000>;
102 reg = <0x40000 0x180000>;
107 reg = <0x1c0000 0xe00000>;
112 reg = <0xfc0000 0x10000>;
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/mobileye/
Dmobileye,eyeq5-olb.yaml46 enum: [ 0, 1 ]
87 pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
329 const: 0
354 reg = <0 0xe00000 0x0 0x400>;
368 reg = <0x0 0xd2003000 0x0 0x1000>;
/linux-6.12.1/arch/arm/boot/dts/intel/ixp/
Dintel-ixp43x-gateworks-gw2358.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x57>;
81 flash@0,0 {
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dm5307sim.h27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
36 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
[all …]
/linux-6.12.1/arch/csky/kernel/probes/
Dsimulate-insn.c18 *ptr = *(&regs->exregs[0] + index - 16); in csky_insn_reg_get_val()
47 *(&regs->exregs[0] + index - 16) = val; in csky_insn_reg_set_val()
72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16()
79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32()
87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16()
97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32()
107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16()
117 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bf32()
125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
[all …]
/linux-6.12.1/drivers/remoteproc/
Dti_k3_dsp_remoteproc.c122 dev_dbg(dev, "mbox msg: 0x%x\n", msg); in k3_dsp_rproc_mbox_callback()
140 dev_dbg(dev, "dropping unknown message 0x%x", msg); in k3_dsp_rproc_mbox_callback()
168 if (ret < 0) in k3_dsp_rproc_kick()
240 kproc->mbox = mbox_request_channel(client, 0); in k3_dsp_rproc_request_mbox()
253 if (ret < 0) { in k3_dsp_rproc_request_mbox()
259 return 0; in k3_dsp_rproc_request_mbox()
325 dev_err(dev, "invalid boot address 0x%x, must be aligned on a 0x%x boundary\n", in k3_dsp_rproc_start()
330 dev_dbg(dev, "booting DSP core using boot addr = 0x%x\n", boot_addr); in k3_dsp_rproc_start()
331 ret = ti_sci_proc_set_config(kproc->tsp, boot_addr, 0, 0); in k3_dsp_rproc_start()
339 return 0; in k3_dsp_rproc_start()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux-6.12.1/net/ipv6/
Dioam6_iptunnel.c25 #define IOAM6_MASK_SHORT_FIELDS 0xff100000
26 #define IOAM6_MASK_WIDE_FIELDS 0xe00000
95 trace->nodelen = 0; in ioam6_validate_trace_hdr()
125 if (err < 0) in ioam6_build_state()
182 atomic_set(&ilwt->pkt_cnt, 0); in ioam6_build_state()
215 tuninfo->pad[0] = IPV6_TLV_PADN; in ioam6_build_state()
233 return 0; in ioam6_build_state()
254 return 0; in ioam6_do_fill()
405 memset(&fl6, 0, sizeof(fl6)); in ioam6_output()
/linux-6.12.1/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux-6.12.1/lib/xz/
Dxz_dec_bcj.c1 // SPDX-License-Identifier: 0BSD
69 * PowerPC 4 0
70 * IA-64 16 0
71 * ARM 4 0
73 * SPARC 4 0
86 return b == 0x00 || b == 0xFF; in bcj_x86_test_msbyte()
94 static const uint8_t mask_to_bit_num[8] = { 0, 1, 2, 2, 3, 3, 3, 3 }; in bcj_x86()
105 return 0; in bcj_x86()
108 for (i = 0; i < size; ++i) { in bcj_x86()
109 if ((buf[i] & 0xFE) != 0xE8) in bcj_x86()
[all …]
/linux-6.12.1/arch/mips/lantiq/xway/
Dsysctrl.c21 #define CGU_IFCCR 0x0018
22 #define CGU_IFCCR_VR9 0x0024
24 #define CGU_SYS 0x0010
26 #define CGU_PCICR 0x0034
27 #define CGU_PCICR_VR9 0x0038
29 #define CGU_EPHY 0x10
33 #define PMU_PWDCR 0x1C
35 #define PMU_PWDSR 0x20
37 #define PMU_PWDCR1 0x24
39 #define PMU_PWDSR1 0x28
[all …]

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