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Searched +full:0 +full:xc0100000 (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu8.h65 #define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
66 #define SMU8_UNBCSR_START_ADDR 0xC0100000
68 #define SMN_MP1_SRAM_START_ADDR 0x10000000
/linux-6.12.1/Documentation/devicetree/bindings/net/
Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/linux-6.12.1/arch/powerpc/include/asm/
Dpage.h112 #define MEMORY_START 0UL
158 * Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
159 * In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
161 * Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
162 * = 0xbc100000 , which is wrong.
164 * Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
218 (unsigned long)(x) & 0x0fffffffffffffffUL; \
265 #define is_kernel_addr(x) ((x) >= 0x8000000000000000ul)
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_0_0_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
Dsmu_7_1_1_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
Dsmu_7_1_2_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
Dsmu_7_1_3_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
Dsmu_7_1_0_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
Dsmu_7_0_1_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dqcm6490-idp.dts44 pinctrl-0 = <&pmic_lcd_bl_en>;
59 pinctrl-0 = <&lcd_disp_bias_en>;
66 pinctrl-0 = <&key_vol_up_default>;
81 reg = <0x0 0x80700000 0x0 0x100000>;
86 reg = <0x0 0x81800000 0x0 0x1e00000>;
91 reg = <0x0 0x84300000 0x0 0x500000>;
96 reg = <0x0 0x84800000 0x0 0x1900000>;
101 reg = <0x0 0x86100000 0x0 0x2800000>;
106 reg = <0x0 0x88900000 0x0 0x1e00000>;
111 reg = <0x0 0x8a700000 0x0 0x700000>;
[all …]
Dqcs6490-rb3gen2.dts76 reg = <0x0 0x80700000 0x0 0x100000>;
81 reg = <0x0 0x81800000 0x0 0x1e00000>;
86 reg = <0x0 0x84300000 0x0 0x500000>;
91 reg = <0x0 0x84800000 0x0 0x1900000>;
96 reg = <0x0 0x86100000 0x0 0x2800000>;
101 reg = <0x0 0x88900000 0x0 0x1e00000>;
106 reg = <0x0 0x8a700000 0x0 0x700000>;
111 reg = <0x0 0x8ae00000 0x0 0x500000>;
116 reg = <0x0 0x8b300000 0x0 0x10000>;
121 reg = <0x0 0x8b310000 0x0 0xa000>;
[all …]