/linux-6.12.1/drivers/gpu/drm/sun4i/ |
D | sun8i_mixer.h | 19 #define SUN8I_MIXER_GLOBAL_CTL 0x0 20 #define SUN8I_MIXER_GLOBAL_STATUS 0x4 21 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8 22 #define SUN8I_MIXER_GLOBAL_SIZE 0xc 24 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0) 26 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0) 28 #define DE2_MIXER_UNIT_SIZE 0x6000 29 #define DE3_MIXER_UNIT_SIZE 0x3000 31 #define DE2_BLD_BASE 0x1000 32 #define DE2_CH_BASE 0x2000 [all …]
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/linux-6.12.1/arch/arm/boot/dts/marvell/ |
D | armada-395.dtsi | 19 reg = <0x18000 0x20>; 24 reg = <0xa8000 0x2000>; 32 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
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D | armada-38x.dtsi | 42 pcie-mem-aperture = <0xe0000000 0x8000000>; 43 pcie-io-aperture = <0xe8000000 0x100000>; 47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 56 clocks = <&coreclk 0>; 62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 66 clocks = <&coreclk 0>; 72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | qoriq-fman3-0-1g-0.dtsi | 3 * QorIQ FMan v3 1g port #0 device tree 11 cell-index = <0x8>; 13 reg = <0x88000 0x1000>; 17 cell-index = <0x28>; 19 reg = <0xa8000 0x1000>; 23 cell-index = <0>; 25 reg = <0xe0000 0x1000>; 34 #size-cells = <0>; 36 reg = <0xe1000 0x1000>; 38 pcsphy0: ethernet-phy@0 { [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/phy/ |
D | qcom-usb-ipq4019-phy.yaml | 30 const: 0 46 #phy-cells = <0>; 48 reg = <0xa8000 0x40>;
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
D | qoriq-fman3-0-10g-2.dtsi | 3 * QorIQ FMan v3 10g port #2 device tree stub [ controller @ offset 0x400000 ] 11 cell-index = <0x8>; 13 reg = <0x88000 0x1000>; 18 cell-index = <0x28>; 20 reg = <0xa8000 0x1000>; 25 cell-index = <0>; 27 reg = <0xe0000 0x1000>; 36 #size-cells = <0>; 38 reg = <0xe1000 0x1000>; 41 pcsphy0: ethernet-phy@0 { [all …]
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D | qoriq-fman-0-1g-0.dtsi | 2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 43 cell-index = <0x28>; 45 reg = <0xa8000 0x1000>; 49 cell-index = <0>; 51 reg = <0xe0000 0x1000>; 59 #size-cells = <0>; 61 reg = <0xe1120 0xee0>; 62 interrupts = <100 2 0 0>; [all …]
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D | qoriq-fman3-0-1g-0.dtsi | 2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 43 cell-index = <0x28>; 45 reg = <0xa8000 0x1000>; 49 cell-index = <0>; 51 reg = <0xe0000 0x1000>; 60 #size-cells = <0>; 62 reg = <0xe1000 0x1000>; 65 pcsphy0: ethernet-phy@0 { [all …]
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D | qoriq-fman3-1-1g-0.dtsi | 2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 43 cell-index = <0x28>; 45 reg = <0xa8000 0x1000>; 49 cell-index = <0>; 51 reg = <0xe0000 0x1000>; 60 #size-cells = <0>; 62 reg = <0xe1000 0x1000>; 65 pcsphy8: ethernet-phy@0 { [all …]
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D | qoriq-fman-1-1g-0.dtsi | 2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 43 cell-index = <0x28>; 45 reg = <0xa8000 0x1000>; 49 cell-index = <0>; 51 reg = <0xe0000 0x1000>; 59 #size-cells = <0>; 61 reg = <0xe1120 0xee0>; 64 reg = <0x8>;
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D | qoriq-fman3-0-10g-0-best-effort.dtsi | 2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 45 cell-index = <0x28>; 47 reg = <0xa8000 0x1000>; 53 cell-index = <0>; 55 reg = <0xe0000 0x1000>; 64 #size-cells = <0>; 66 reg = <0xe1000 0x1000>; 69 pcsphy0: ethernet-phy@0 { [all …]
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D | t4240si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 65 pcie@0 { 70 reg = <0 0 0 0 0>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | fsl,fman-port.yaml | 72 reg = <0xa8000 0x1000>; 73 cell-index = <0x28>;
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D | fsl,fman.yaml | 22 FMan block. The offset is 0xc4 from the beginning of the 23 Frame Processing Manager memory map (0xc3000 from the 38 DEVDISR[1] 1 0 43 DCFG_DEVDISR2[6] 1 0 50 DCFG_CCSR_DEVDISR2[24] 1 0 156 reg = <0x400000 0x100000>; 157 ranges = <0 0x400000 0x100000>; 165 fsl,qman-channel-range = <0x40 0xc>; 167 muram@0 { 169 reg = <0x0 0x28000>; [all …]
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/linux-6.12.1/arch/arm/mach-imx/ |
D | mx3x.h | 36 #define MX3x_L2CC_BASE_ADDR 0x30000000 42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000 44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) 47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) 48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) 49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) 50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) 51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) [all …]
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/linux-6.12.1/arch/arm/boot/dts/qcom/ |
D | qcom-ipq4019.dtsi | 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 26 reg = <0x87e00000 0x080000>; 31 reg = <0x87e80000 0x180000>; 45 #size-cells = <0>; 46 cpu@0 { 53 reg = <0x0>; 55 clock-frequency = <0>; 67 reg = <0x1>; 69 clock-frequency = <0>; [all …]
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/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7996/ |
D | mmio.c | 21 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } }, 22 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } }, 23 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } }, 24 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } }, 25 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } }, 26 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } }, 27 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, 28 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, 29 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, 30 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } }, [all …]
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/linux-6.12.1/drivers/net/wireless/ath/ath10k/ |
D | coredump.c | 19 {0x800, 0x810}, 20 {0x820, 0x82C}, 21 {0x830, 0x8F4}, 22 {0x90C, 0x91C}, 23 {0xA14, 0xA18}, 24 {0xA84, 0xA94}, 25 {0xAA8, 0xAD4}, 26 {0xADC, 0xB40}, 27 {0x1000, 0x10A4}, 28 {0x10BC, 0x111C}, [all …]
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | am437x-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x44c00000 */ [all …]
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D | am33xx-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x44c00000 */ [all …]
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D | omap5-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */ [all …]
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D | omap4-l4.dtsi | 2 &l4_cfg { /* 0x4a000000 */ 5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; 7 reg = <0x4a000000 0x800>, 8 <0x4a000800 0x800>, 9 <0x4a001000 0x1000>; 13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */ [all …]
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D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 16 segment@0 { /* 0x4a000000 */ 20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ [all …]
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/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7915/ |
D | mmio.c | 21 [INT_SOURCE_CSR] = 0xd7010, 22 [INT_MASK_CSR] = 0xd7014, 23 [INT1_SOURCE_CSR] = 0xd7088, 24 [INT1_MASK_CSR] = 0xd708c, 25 [INT_MCU_CMD_SOURCE] = 0xd51f0, 26 [INT_MCU_CMD_EVENT] = 0x3108, 27 [WFDMA0_ADDR] = 0xd4000, 28 [WFDMA0_PCIE1_ADDR] = 0xd8000, 29 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 30 [CBTOP1_PHY_END] = 0x77ffffff, [all …]
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/linux-6.12.1/drivers/phy/microchip/ |
D | sparx5_serdes.c | 31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c 34 SPX5_SD10G28_CMU_MAIN = 0, 353 .cfg_en_adv = 0, 355 .cfg_en_dly = 0, 356 .cfg_tap_adv_3_0 = 0, 358 .cfg_tap_dly_4_0 = 0, 359 .cfg_eq_c_force_3_0 = 0xf, 368 .cfg_tap_adv_3_0 = 0, 370 .cfg_tap_dly_4_0 = 0x10, 371 .cfg_eq_c_force_3_0 = 0xf, [all …]
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