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/linux-6.12.1/lib/
Dtest_xarray.c20 void xa_dump(const struct xarray *xa) { } in xa_dump() argument
23 #define XA_BUG_ON(xa, x) do { \ argument
27 xa_dump(xa); \
32 } while (0)
40 static void *xa_store_index(struct xarray *xa, unsigned long index, gfp_t gfp) in xa_store_index() argument
42 return xa_store(xa, index, xa_mk_index(index), gfp); in xa_store_index()
45 static void xa_insert_index(struct xarray *xa, unsigned long index) in xa_insert_index() argument
47 XA_BUG_ON(xa, xa_insert(xa, index, xa_mk_index(index), in xa_insert_index()
48 GFP_KERNEL) != 0); in xa_insert_index()
51 static void xa_alloc_index(struct xarray *xa, unsigned long index, gfp_t gfp) in xa_alloc_index() argument
[all …]
Dxarray.c20 * @xa is used to refer to the entire xarray.
33 static inline unsigned int xa_lock_type(const struct xarray *xa) in xa_lock_type() argument
35 return (__force unsigned int)xa->xa_flags & 3; in xa_lock_type()
58 static inline bool xa_track_free(const struct xarray *xa) in xa_track_free() argument
60 return xa->xa_flags & XA_FLAGS_TRACK_FREE; in xa_track_free()
63 static inline bool xa_zero_busy(const struct xarray *xa) in xa_zero_busy() argument
65 return xa->xa_flags & XA_FLAGS_ZERO_BUSY; in xa_zero_busy()
68 static inline void xa_mark_set(struct xarray *xa, xa_mark_t mark) in xa_mark_set() argument
70 if (!(xa->xa_flags & XA_FLAGS_MARK(mark))) in xa_mark_set()
71 xa->xa_flags |= XA_FLAGS_MARK(mark); in xa_mark_set()
[all …]
/linux-6.12.1/include/linux/
Dxarray.h40 * 0-62: Sibling entries
60 WARN_ON((long)v < 0); in xa_mk_value()
91 * @tag: Tag value (0, 1 or 3).
94 * of storing value entries. Three tags are available (0, 1 and 3).
140 * Internal entries are used for a number of purposes. Entries 0-255 are
141 * used for sibling entries (only 0-62 are used by the current code). 256
217 * the errno from the pointer value, or returns 0 if the pointer does not
221 * Return: A negative errno or 0.
228 return 0; in xa_err()
239 * * xa_limit_32b - [0 - UINT_MAX]
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
/linux-6.12.1/tools/testing/radix-tree/
Dmultiorder.c15 static int item_insert_order(struct xarray *xa, unsigned long index, in item_insert_order() argument
18 XA_STATE_ORDER(xas, xa, index, order); in item_insert_order()
28 return 0; in item_insert_order()
34 void multiorder_iteration(struct xarray *xa) in multiorder_iteration() argument
36 XA_STATE(xas, xa, 0); in multiorder_iteration()
41 int index[NUM_ENTRIES] = {0, 2, 4, 8, 16, 32, 34, 36, 64, 72, 128}; in multiorder_iteration()
42 int order[NUM_ENTRIES] = {1, 1, 2, 3, 4, 1, 0, 1, 3, 0, 7}; in multiorder_iteration()
46 for (i = 0; i < NUM_ENTRIES; i++) { in multiorder_iteration()
47 err = item_insert_order(xa, index[i], order[i]); in multiorder_iteration()
51 for (j = 0; j < 256; j++) { in multiorder_iteration()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux-6.12.1/drivers/infiniband/core/
Drestrack.c21 * Return: 0 on success
34 for (i = 0; i < RDMA_RESTRACK_MAX; i++) in rdma_restrack_init()
35 xa_init_flags(&rt[i].xa, XA_FLAGS_ALLOC); in rdma_restrack_init()
37 return 0; in rdma_restrack_init()
49 for (i = 0 ; i < RDMA_RESTRACK_MAX; i++) { in rdma_restrack_clean()
50 struct xarray *xa = &dev->res[i].xa; in rdma_restrack_clean() local
52 WARN_ON(!xa_empty(xa)); in rdma_restrack_clean()
53 xa_destroy(xa); in rdma_restrack_clean()
69 XA_STATE(xas, &rt->xa, 0); in rdma_restrack_count()
70 u32 cnt = 0; in rdma_restrack_count()
[all …]
/linux-6.12.1/net/core/
Dxdp.c25 #define REG_STATE_NEW 0x0
26 #define REG_STATE_REGISTERED 0x1
27 #define REG_STATE_UNREGISTERED 0x2
28 #define REG_STATE_UNUSED 0x3
32 #define MEM_ID_MAX 0xFFFE
54 const struct xdp_mem_allocator *xa = ptr; in xdp_mem_id_cmp() local
57 return xa->mem.id != mem_id; in xdp_mem_id_cmp()
74 struct xdp_mem_allocator *xa; in __xdp_mem_allocator_rcu_free() local
76 xa = container_of(rcu, struct xdp_mem_allocator, rcu); in __xdp_mem_allocator_rcu_free()
79 ida_free(&mem_id_pool, xa->mem.id); in __xdp_mem_allocator_rcu_free()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/umc/
Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
Ddpcs_3_1_4_sh_mask.h33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1
35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3
37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7
39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9
41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa
42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb
[all …]
Ddpcs_4_2_2_sh_mask.h14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
Ddpcs_4_2_0_sh_mask.h27 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
28 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
30 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
31 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
36 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
37 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
39 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
40 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
45 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
46 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb/
Dvsc7326_reg.h14 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
17 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
18 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
19 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
20 #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
21 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
22 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
23 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
24 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
25 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]
/linux-6.12.1/include/trace/events/
Dxdp.h111 u32 ifindex = 0, map_index = index;
114 /* Just leave to_ifindex to 0 if do broadcast redirect,
121 map_index = 0;
160 trace_xdp_redirect(dev, xdp, NULL, 0, BPF_MAP_TYPE_UNSPEC, INT_MAX, to)
166 trace_xdp_redirect(dev, xdp, to, 0, map_type, map_id, index)
318 __MEM_TYPE_MAP(__MEM_TYPE_SYM_FN) { -1, 0 }
323 TP_PROTO(const struct xdp_mem_allocator *xa),
325 TP_ARGS(xa),
328 __field(const struct xdp_mem_allocator *, xa)
335 __entry->xa = xa;
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux-6.12.1/drivers/infiniband/sw/rxe/
Drxe_pool.c97 memset(pool, 0, sizeof(*pool)); in rxe_pool_init()
107 atomic_set(&pool->num_elem, 0); in rxe_pool_init()
109 xa_init_flags(&pool->xa, XA_FLAGS_ALLOC); in rxe_pool_init()
116 WARN_ON(!xa_empty(&pool->xa)); in rxe_pool_cleanup()
141 err = xa_alloc_cyclic(&pool->xa, &elem->index, NULL, pool->limit, in __rxe_add_to_pool()
143 if (err < 0) in __rxe_add_to_pool()
146 return 0; in __rxe_add_to_pool()
156 struct xarray *xa = &pool->xa; in rxe_pool_get_index() local
160 elem = xa_load(xa, index); in rxe_pool_get_index()
180 struct xarray *xa = &pool->xa; in __rxe_cleanup() local
[all …]
/linux-6.12.1/drivers/phy/starfive/
Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_reg_sr.c35 xa_destroy(&sr->xa); in reg_sr_fini()
37 memset(&sr->pool, 0, sizeof(sr->pool)); in reg_sr_fini()
42 xa_init(&sr->xa); in xe_reg_sr_init()
43 memset(&sr->pool, 0, sizeof(sr->pool)); in xe_reg_sr_init()
98 struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx); in xe_reg_sr_add()
111 return 0; in xe_reg_sr_add()
121 ret = xa_err(xa_store(&sr->xa, idx, pentry, GFP_KERNEL)); in xe_reg_sr_add()
125 return 0; in xe_reg_sr_add()
169 val = 0; in apply_one_mmio()
178 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); in apply_one_mmio()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
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