Home
last modified time | relevance | path

Searched +full:0 +full:x820 (Results 1 – 25 of 151) sorted by relevance

1234567

/linux-6.12.1/Documentation/i2c/busses/
Dscx200_acb.rst15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
/linux-6.12.1/arch/arm/mm/
Dcache-tauros3.h20 #define TAUROS3_EVENT_CNT2_CFG 0x224
21 #define TAUROS3_EVENT_CNT2_VAL 0x228
22 #define TAUROS3_INV_ALL 0x780
23 #define TAUROS3_CLEAN_ALL 0x784
24 #define TAUROS3_AUX2_CTRL 0x820
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dtoshiba,tmpv770x-pipllct.yaml43 #clock-cells = <0>;
52 reg = <0 0x24220000 0 0x820>;
Dfsl,qoriq-clock.yaml88 0 sysclk must be 0
91 3 fman 0 for fm1, 1 for fm2
94 5 coreclk must be 0
116 '^mux[0-9]@[a-f0-9]+$':
124 '^pll[0-9]@[a-f0-9]+$':
144 reg = <0xe1000 0x1000>;
153 reg = <0xe1000 0x1000>;
154 ranges = <0x0 0xe1000 0x1000>;
163 #clock-cells = <0>;
168 reg = <0x800 0x4>;
[all …]
/linux-6.12.1/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
50 /* 3. Page8(0x800) */
52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
55 #define rFPGA0_XA_HSSIParameter2 0x824
56 #define rFPGA0_XB_HSSIParameter1 0x828
57 #define rFPGA0_XB_HSSIParameter2 0x82c
58 #define rTxAGC_B_Rate18_06 0x830
[all …]
/linux-6.12.1/drivers/watchdog/
Dnpcm_wdt.c16 #define NPCM_WTCR 0x1C
25 #define NPCM_WTR BIT(0) /* Reset counter */
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Dvncr_mapping.h10 #define VNCR_VTTBR_EL2 0x020
11 #define VNCR_VTCR_EL2 0x040
12 #define VNCR_VMPIDR_EL2 0x050
13 #define VNCR_CNTVOFF_EL2 0x060
14 #define VNCR_HCR_EL2 0x078
15 #define VNCR_HSTR_EL2 0x080
16 #define VNCR_VPIDR_EL2 0x088
17 #define VNCR_TPIDR_EL2 0x090
18 #define VNCR_HCRX_EL2 0x0A0
19 #define VNCR_VNCR_EL2 0x0B0
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
/linux-6.12.1/include/dt-bindings/pinctrl/
Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dqoriq-fman3-1.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
/linux-6.12.1/include/linux/usb/
Dusb338x.h19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dphy-miphy28lp.txt56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
[all …]
/linux-6.12.1/drivers/net/wireless/rsi/
Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/msm/
Dqcom,sm6375-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x05e00000 0x1000>;
100 iommus = <&apps_smmu 0x820 0x2>;
107 reg = <0x05e01000 0x8e030>,
108 <0x05eb0000 0x2008>;
133 interrupts = <0>;
137 #size-cells = <0>;
139 port@0 {
[all …]
Dqcom,sm8350-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
99 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
100 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
112 iommus = <&apps_smmu 0x820 0x402>;
124 reg = <0x0ae01000 0x8f000>,
125 <0x0aeb0000 0x2008>;
[all …]
/linux-6.12.1/drivers/soc/imx/
Dsoc-imx.c16 #define IIM_UID 0x820
18 #define OCOTP_UID_H 0x420
19 #define OCOTP_UID_L 0x410
21 #define OCOTP_ULP_UID_1 0x4b0
22 #define OCOTP_ULP_UID_2 0x4c0
23 #define OCOTP_ULP_UID_3 0x4d0
24 #define OCOTP_ULP_UID_4 0x4e0
34 u64 soc_uid = 0; in imx_soc_device_init()
41 return 0; in imx_soc_device_init()
155 soc_uid = val & 0xffff; in imx_soc_device_init()
[all …]
/linux-6.12.1/drivers/reset/sti/
Dreset-stih407.c25 /* Powerdown requests control 0 */
26 #define SYSCFG_5000 0x0
27 #define SYSSTAT_5500 0x7d0
29 #define SYSCFG_5001 0x4
30 #define SYSSTAT_5501 0x7d4
33 #define SYSCFG_4032 0x80
34 #define SYSSTAT_4520 0x820
35 #define SYSCFG_4002 0x8
39 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
46 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
[all …]
/linux-6.12.1/drivers/reset/hisilicon/
Dhi6220_reset.c22 #define PERIPH_ASSERT_OFFSET 0x300
23 #define PERIPH_DEASSERT_OFFSET 0x304
24 #define PERIPH_MAX_INDEX 0x509
26 #define SC_MEDIA_RSTEN 0x052C
27 #define SC_MEDIA_RSTDIS 0x0530
49 u32 offset = idx & 0xff; in hi6220_peripheral_assert()
50 u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_assert()
61 u32 offset = idx & 0xff; in hi6220_peripheral_deassert()
62 u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_deassert()
95 #define AO_SCTRL_SC_PW_CLKEN0 0x800
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh3/
Dsetup-sh7710.c19 UNUSED = 0,
33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41 INTC_VECT(IPSEC, 0xbe0),
43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
[all …]
Dsetup-sh7705.c20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dtable.c8 0x800, 0x80040000,
9 0x804, 0x00000003,
10 0x808, 0x0000FC00,
11 0x80C, 0x0000000A,
12 0x810, 0x10001331,
13 0x814, 0x020C3D10,
14 0x818, 0x02200385,
15 0x81C, 0x00000000,
16 0x820, 0x01000100,
17 0x824, 0x00190204,
[all …]
/linux-6.12.1/drivers/phy/ralink/
Dphy-ralink-usb.c22 #define RT_SYSC_REG_SYSCFG1 0x014
23 #define RT_SYSC_REG_CLKCFG1 0x030
24 #define RT_SYSC_REG_USB_PHY_CFG 0x05c
26 #define OFS_U2_PHY_AC0 0x800
27 #define OFS_U2_PHY_AC1 0x804
28 #define OFS_U2_PHY_AC2 0x808
29 #define OFS_U2_PHY_ACR0 0x810
30 #define OFS_U2_PHY_ACR1 0x814
31 #define OFS_U2_PHY_ACR2 0x818
32 #define OFS_U2_PHY_ACR3 0x81C
[all …]
/linux-6.12.1/include/linux/mfd/
Drz-mtu3.h13 #define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
17 #define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
23 #define RZ_MTU3_TCNTSA 0x020 /* Timer subcounter A */
24 #define RZ_MTU3_TCNTSB 0x820 /* Timer subcounter B */
[all …]
/linux-6.12.1/drivers/gpu/drm/sun4i/
Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]

1234567