Searched +full:0 +full:x802000 (Results 1 – 4 of 4) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | sysctrl.yaml | 58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
116 ranges = <0 0x802000 0x1000>;
117 reg = <0x802000 0x1000>;
119 smp-offset = <0x31c>;
120 resume-offset = <0x308>;
121 reboot-offset = <0x4>;
123 clock: clock@0 {
125 reg = <0 0x10000>;
133 reg = <0x10000000 0x1000>;
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/hisilicon/ |
| D | hi3620.dtsi | 27 #clock-cells = <0>;
34 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x0>;
72 ranges = <0 0xfc000000 0x2000000>;
76 reg = <0x100000 0x100000>;
77 interrupts = <0 15 4>;
85 #address-cells = <0>;
88 reg = <0x1000 0x1000>, <0x100 0x100>;
95 ranges = <0 0x802000 0x1000>;
[all …]
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| /linux-6.12.1/arch/x86/pci/ |
| D | olpc.c | 33 * the size of the region by writing ~0 to a base address register
38 * ~0 to a base address register.
41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
42 0x0, 0x0, 0x0, 0x0,
43 0x0, 0x0, 0x0, 0x0,
45 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
46 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
47 0x0, 0x0, 0x0, 0x28100b,
48 0x0, 0x0, 0x0, 0x0,
49 0x0, 0x0, 0x0, 0x0,
[all …]
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| /linux-6.12.1/sound/pci/pcxhr/ |
| D | pcxhr_core.c | 23 #define PCXHR_PLX_OFFSET_MIN 0x40
24 #define PCXHR_PLX_MBOX0 0x40
25 #define PCXHR_PLX_MBOX1 0x44
26 #define PCXHR_PLX_MBOX2 0x48
27 #define PCXHR_PLX_MBOX3 0x4C
28 #define PCXHR_PLX_MBOX4 0x50
29 #define PCXHR_PLX_MBOX5 0x54
30 #define PCXHR_PLX_MBOX6 0x58
31 #define PCXHR_PLX_MBOX7 0x5C
32 #define PCXHR_PLX_L2PCIDB 0x64
[all …]
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