Searched +full:0 +full:x7000f400 (Results 1 – 6 of 6) sorted by relevance
16 #define TEGRA_IRAM_BASE 0x4000000019 #define TEGRA_ARM_PERIF_BASE 0x5004000022 #define TEGRA_ARM_INT_DIST_BASE 0x5004100025 #define TEGRA_TMR1_BASE 0x6000500028 #define TEGRA_TMR2_BASE 0x6000500831 #define TEGRA_TMRUS_BASE 0x6000501034 #define TEGRA_TMR3_BASE 0x6000505037 #define TEGRA_TMR4_BASE 0x6000505840 #define TEGRA_CLK_RESET_BASE 0x6000600043 #define TEGRA_FLOW_CTRL_BASE 0x60007000[all …]
90 reg = <0x7000f000 0x400>;94 interrupts = <0 77 4>;103 reg = <0x7000f400 0x400>;104 interrupts = <0 78 4>;111 #interconnect-cells = <0>;116 reg = <0x6000c800 0x400>;117 interrupts = <0 45 4>;
38 const: 041 const: 0145 "^emc-table@[0-9]+$":165 const: 0172 "^emc-table@[0-9]+$":199 reg = <0x7000f400 0x400>;200 interrupts = <0 78 4>;207 #interconnect-cells = <0>;209 #size-cells = <0>;213 emc-tables@0 {[all …]
35 const: 053 "^emc-timings-[0-9]+$":62 "^timing-[0-9]+$":75 minimum: 091 Mode Register 0.98 minimum: 0239 reg = <0x7000f400 0x400>;240 interrupts = <0 78 4>;247 #interconnect-cells = <0>;255 nvidia,emc-auto-cal-interval = <0x001fffff>;[all …]
17 memory@0 {19 reg = <0 0>;24 reg = <0x40000000 0x40000>;27 ranges = <0 0x40000000 0x40000>;30 reg = <0x400 0x3fc00>;37 reg = <0x50000000 0x00024000>;51 ranges = <0x54000000 0x54000000 0x04000000>;55 reg = <0x54040000 0x00040000>;67 reg = <0x54080000 0x00040000>;79 reg = <0x540c0000 0x00040000>;[all …]
20 reg = <0x80000000 0x0>;26 reg = <0x00003000 0x00000800>, /* PADS registers */27 <0x00003800 0x00000200>, /* AFI registers */28 <0x10000000 0x10000000>; /* configuration space */35 interrupt-map-mask = <0 0 0 0>;36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;38 bus-range = <0x00 0xff>;42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */[all …]