Searched +full:0 +full:x70008000 (Results 1 – 6 of 6) sorted by relevance
10 #define CG6_FBC 0x7000000011 #define CG6_TEC 0x7000100012 #define CG6_BTREGS 0x7000200013 #define CG6_FHC 0x7000400014 #define CG6_THC 0x7000500015 #define CG6_ROM 0x7000600016 #define CG6_RAM 0x7001600017 #define CG6_DHC 0x8000000019 #define CG3_MMAP_OFFSET 0x400000022 #define TCX_RAM8BIT 0x00000000[all …]
47 reg = <0x70008000 0x100>;54 nand@0 {55 reg = <0>;62 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
117 default: 0136 default: 0146 default: 0156 default: 0204 reg = <0x70004000 0x4000>;211 reg = <0x70008000 0x4000>;213 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */214 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
13 #define FBTYPE_SUN1BW 0 /* mono */58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)61 int index; /* first element (0 origin) */124 #define FB_WID_SHARED_8 0196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */225 #define CG6_FBC 0x70000000226 #define CG6_TEC 0x70001000227 #define CG6_BTREGS 0x70002000228 #define CG6_FHC 0x70004000229 #define CG6_THC 0x70005000[all …]
46 reg = <0xe0000000 0x4000>;52 #clock-cells = <0>;58 #clock-cells = <0>;59 clock-frequency = <0>;64 #clock-cells = <0>;65 clock-frequency = <0>;70 #clock-cells = <0>;77 #size-cells = <0>;78 cpu: cpu@0 {81 reg = <0>;[all …]
17 memory@0 {19 reg = <0 0>;24 reg = <0x40000000 0x40000>;27 ranges = <0 0x40000000 0x40000>;30 reg = <0x400 0x3fc00>;37 reg = <0x50000000 0x00024000>;51 ranges = <0x54000000 0x54000000 0x04000000>;55 reg = <0x54040000 0x00040000>;67 reg = <0x54080000 0x00040000>;79 reg = <0x540c0000 0x00040000>;[all …]