Searched +full:0 +full:x70002000 (Results 1 – 5 of 5) sorted by relevance
10 #define CG6_FBC 0x7000000011 #define CG6_TEC 0x7000100012 #define CG6_BTREGS 0x7000200013 #define CG6_FHC 0x7000400014 #define CG6_THC 0x7000500015 #define CG6_ROM 0x7000600016 #define CG6_RAM 0x7001600017 #define CG6_DHC 0x8000000019 #define CG3_MMAP_OFFSET 0x400000022 #define TCX_RAM8BIT 0x00000000[all …]
72 reg = <0x70002000 0x200>;80 nvidia,codec-sync-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
13 #define FBTYPE_SUN1BW 0 /* mono */58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)61 int index; /* first element (0 origin) */124 #define FB_WID_SHARED_8 0196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */225 #define CG6_FBC 0x70000000226 #define CG6_TEC 0x70001000227 #define CG6_BTREGS 0x70002000228 #define CG6_FHC 0x70004000229 #define CG6_THC 0x70005000[all …]
8 #define MT_MCU_WFDMA1_BASE 0x300011 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)17 #define MT_PLE_BASE 0x820c000020 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))[all …]
17 memory@0 {19 reg = <0 0>;24 reg = <0x40000000 0x40000>;27 ranges = <0 0x40000000 0x40000>;30 reg = <0x400 0x3fc00>;37 reg = <0x50000000 0x00024000>;51 ranges = <0x54000000 0x54000000 0x04000000>;55 reg = <0x54040000 0x00040000>;67 reg = <0x54080000 0x00040000>;79 reg = <0x540c0000 0x00040000>;[all …]