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/linux-6.12.1/Documentation/devicetree/bindings/misc/
Dnvidia,tegra20-apbmisc.yaml49 reg = <0x70000800 0x64>, /* Chip revision */
50 <0x70000008 0x04>; /* Strapping options */
/linux-6.12.1/arch/mips/include/asm/
Delf.h21 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
22 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
23 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
24 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
25 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
26 #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */
27 #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
28 #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */
29 #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */
32 #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */
[all …]
/linux-6.12.1/drivers/soc/tegra/fuse/
Dtegra-apbmisc.c19 #define FUSE_SKU_INFO 0x10
21 #define ERD_ERR_CONFIG 0x120c
22 #define ERD_MASK_INBAND_ERR 0x1
26 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
28 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
44 return (tegra_read_chipid() >> 8) & 0xff; in tegra_get_chip_id()
49 return (tegra_read_chipid() >> 4) & 0xf; in tegra_get_major_rev()
54 return (tegra_read_chipid() >> 16) & 0xf; in tegra_get_minor_rev()
59 return (tegra_read_chipid() >> 20) & 0xf; in tegra_get_platform()
69 if (tegra_get_platform() == 0) in tegra_is_silicon()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
[all …]
Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
[all …]
Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]